aboutsummaryrefslogtreecommitdiff
path: root/hw/vexpress.c
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2012-07-16 11:15:58 +0100
committerPeter Maydell <petmay01@cam-vm-266.(none)>2012-07-16 13:03:59 +0100
commit4860a89d1535ef8d4b9418e899a929b8cedeb44f (patch)
treed2d38d90ecd234ffe976392e3a39ca23b70d8260 /hw/vexpress.c
parent3ecd51f261b5c8a9edbad50e7a6a7550386fddce (diff)
downloadqemu-arm-4860a89d1535ef8d4b9418e899a929b8cedeb44f.tar.gz
hw/vexpress.c: Allow >4GB of RAM for Cortex-A15 daughterboardboot-fix-int-sizes
Now that we have LPAE support and can handle passing 64 bit RAM sizes to Linux via the device tree, we can lift the restriction in the Versatile Express A15 daughterboard model on not having more than 2GB of RAM. Allow up to 30GB, which is the maximum that can fit in the address map before running into the (unmodelled) aliases of the first 2GB. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/vexpress.c')
-rw-r--r--hw/vexpress.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 8072c5ada9..b2dc8a5ab3 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -284,9 +284,16 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
- if (ram_size > 0x80000000) {
- fprintf(stderr, "vexpress-a15: cannot model more than 2GB RAM\n");
- exit(1);
+ {
+ /* We have to use a separate 64 bit variable here to avoid the gcc
+ * "comparison is always false due to limited range of data type"
+ * warning if we are on a host where ram_addr_t is 32 bits.
+ */
+ uint64_t rsz = ram_size;
+ if (rsz > (30ULL * 1024 * 1024 * 1024)) {
+ fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
+ exit(1);
+ }
}
memory_region_init_ram(ram, "vexpress.highmem", ram_size);