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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-06-03 17:17:42 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-06-03 17:17:42 +0100
commitc4f08ffe134810307cebd66f2cbcffe5cd707915 (patch)
tree677f0d801a2fa20dab49fe26c10846e6148006a4 /hw/ssi
parente100f3be0cccc58692b3988ec2e35cd8b906ca05 (diff)
xilinx_spips: Implement automatic CS
Implement the automatic CS control feature. If the MANUAL_CS bit is cleared then the chip select stay de-asserted as long as the tx FIFO is empty. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1d67383adc42761af715a93f161344b9284dfc9a.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi')
-rw-r--r--hw/ssi/xilinx_spips.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 0c04ec9486..631d010cd9 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -190,6 +190,12 @@ static inline int num_effective_busses(XilinxSPIPS *s)
s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
}
+static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field)
+{
+ return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS
+ || !fifo8_is_empty(&s->tx_fifo));
+}
+
static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
{
int i, j;
@@ -202,14 +208,15 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
int cs_to_set = (j * s->num_cs + i + upage) %
(s->num_cs * s->num_busses);
- if (~field & (1 << i) && !found) {
+ if (xilinx_spips_cs_is_set(s, i, field) && !found) {
DB_PRINT("selecting slave %d\n", i);
qemu_set_irq(s->cs_lines[cs_to_set], 0);
} else {
+ DB_PRINT("deselecting slave %d\n", i);
qemu_set_irq(s->cs_lines[cs_to_set], 1);
}
}
- if (~field & (1 << i)) {
+ if (xilinx_spips_cs_is_set(s, i, field)) {
found = true;
}
}
@@ -451,12 +458,13 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
}
s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
no_reg_update:
+ xilinx_spips_update_cs_lines(s);
if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
(fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {
xilinx_spips_flush_txfifo(s);
}
- xilinx_spips_update_ixr(s);
xilinx_spips_update_cs_lines(s);
+ xilinx_spips_update_ixr(s);
}
static const MemoryRegionOps spips_ops = {
@@ -510,7 +518,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
fifo8_reset(&s->rx_fifo);
s->regs[R_CONFIG] &= ~CS;
- s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS;
+ s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS;
xilinx_spips_update_cs_lines(s);
/* instruction */
@@ -534,6 +542,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
DB_PRINT("pushing dummy byte\n");
fifo8_push(&s->tx_fifo, 0);
}
+ xilinx_spips_update_cs_lines(s);
xilinx_spips_flush_txfifo(s);
fifo8_reset(&s->rx_fifo);
@@ -545,6 +554,7 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4);
cache_entry++;
}
+ xilinx_spips_update_cs_lines(s);
s->regs[R_CONFIG] |= CS;
xilinx_spips_update_cs_lines(s);