diff options
| author | Artyom Tarasenko <atar4qemu@googlemail.com> | 2010-06-21 20:23:21 +0200 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-06-27 19:06:44 +0300 |
| commit | 94c5f455d3dc2222e0f793928eccf45ab968460e (patch) | |
| tree | ab20707707d56a5c3cf19324a09863a77eb3ae35 /hw/slavio_intctl.c | |
| parent | 3a5c16fcb821beab17d9e0d334bda4927000180c (diff) | |
mask all interrupts when MASTER_DISABLE is set
The MASTER_DISABLE bit (aka mask-all) masks all the interrupts.
According to Sun-4M System Architecture
"The level–15 interrupt sources [...] are maskable with the Interrupt Target
Mask Register. While these interrupts are considered ’non–maskable’ within
the SPARC IU, a mask capability is provided to allow the boot firmware
to establish a basic environment before receiving any level–15 interrupts,
which are non–maskable within SPARC. A mask–all bit is provided to allow
disabling of all external interrupts during change of the CIT."
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/slavio_intctl.c')
| -rw-r--r-- | hw/slavio_intctl.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index b76d3acadd..10362a3655 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -289,9 +289,12 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) } } - /* Level 15 and CPU timer interrupts are not maskable */ - pil_pending |= s->slaves[i].intreg_pending & - (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); + /* Level 15 and CPU timer interrupts are only masked when + the MASTER_DISABLE bit is set */ + if (!(s->intregm_disabled & MASTER_DISABLE)) { + pil_pending |= s->slaves[i].intreg_pending & + (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); + } /* Add soft interrupts */ pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16; |