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authorMarkus Armbruster <armbru@redhat.com>2020-07-07 18:05:54 +0200
committerMarkus Armbruster <armbru@redhat.com>2020-07-10 15:18:08 +0200
commit5325cc34a2ca985283134c7e264be7851b112d4e (patch)
treeba4fb68122e2dcf8860552167c56f97dc962cb00 /hw/riscv
parent1c94a351644fb2555f34e63c8ddc29f70bd4803a (diff)
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in an unusual order: void object_property_set_FOO(Object *obj, FOO_TYPE value, const char *name, Error **errp) Having to pass value before name feels grating. Swap them. Same for object_property_set(), object_property_get(), and object_property_parse(). Convert callers with this Coccinelle script: @@ identifier fun = { object_property_get, object_property_parse, object_property_set_str, object_property_set_link, object_property_set_bool, object_property_set_int, object_property_set_uint, object_property_set, object_property_set_qobject }; expression obj, v, name, errp; @@ - fun(obj, v, name, errp) + fun(obj, name, v, errp) Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Convert that one manually. Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Convert manually. Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused by RXCPU being used both as typedef and function-like macro there. Convert manually. The other files using RXCPU that way don't need conversion. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200707160613.848843-27-armbru@redhat.com> [Straightforwad conflict with commit 2336172d9b "audio: set default value for pcspk.iobase property" resolved]
Diffstat (limited to 'hw/riscv')
-rw-r--r--hw/riscv/opentitan.c4
-rw-r--r--hw/riscv/sifive_e.c4
-rw-r--r--hw/riscv/sifive_u.c6
-rw-r--r--hw/riscv/spike.c4
-rw-r--r--hw/riscv/virt.c4
5 files changed, 11 insertions, 11 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 5fce455d30..7003b1f62d 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -108,9 +108,9 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
MemoryRegion *sys_mem = get_system_memory();
Error *err = NULL;
- object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
+ object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1b2e95a977..f2df06cc43 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -175,7 +175,7 @@ static void sifive_e_soc_init(Object *obj)
SiFiveESoCState *s = RISCV_E_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
- object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
TYPE_SIFIVE_GPIO);
@@ -190,7 +190,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SiFiveESoCState *s = RISCV_E_SOC(dev);
MemoryRegion *sys_mem = get_system_memory();
- object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
+ object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7b9e7fdc7f..e70253d58f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -383,8 +383,8 @@ static void sifive_u_machine_init(MachineState *machine)
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
- object_property_set_uint(OBJECT(&s->soc), s->serial, "serial",
- &error_abort);
+ object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
+ &error_abort);
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* register RAM */
@@ -708,7 +708,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem), nd);
}
- object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
+ object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), &err)) {
error_propagate(errp, err);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 3c87e04fdc..c107bf3ba1 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -171,9 +171,9 @@ static void spike_board_init(MachineState *machine)
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
TYPE_RISCV_HART_ARRAY);
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+ object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
&error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 616db6f5ac..f7630c8a89 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -487,9 +487,9 @@ static void virt_machine_init(MachineState *machine)
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
TYPE_RISCV_HART_ARRAY);
- object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+ object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
&error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);