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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-10 14:29:45 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-10 14:29:45 +0000
commit5c130f659b20d53667e07957ebaa3e656f72b276 (patch)
tree1fce52bae1cfdb3f46599277634769cd50782cb0 /hw/ppc405.h
parentd397abbdbe68715ec86b4392e4e6384db64d029d (diff)
Yet more phys_ram_base elimination.
Signed-off-by: Paul Brook <paul@cofdesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7067 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/ppc405.h')
-rw-r--r--hw/ppc405.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/ppc405.h b/hw/ppc405.h
index eebcef30cd..a18e9480fa 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -78,7 +78,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irq,
CharDriverState *chr);
/* On Chip Memory */
-void ppc405_ocm_init (CPUState *env, unsigned long offset);
+void ppc405_ocm_init (CPUState *env);
/* I2C controller */
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset, qemu_irq irq);
@@ -91,11 +91,11 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
- ram_addr_t *offsetp, int do_init);
+ int do_init);
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
- ram_addr_t *offsetp, int do_init);
+ int do_init);
/* IBM STBxxx microcontrollers */
CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],