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authorAlexander Graf <agraf@suse.de>2010-12-08 12:05:40 +0100
committerBlue Swirl <blauwirbel@gmail.com>2010-12-11 15:24:25 +0000
commit6ebf5905f4a664a873cf7f49094960f08cb3a2d5 (patch)
tree4491565c563b2d3d60dc97e895b30278cb16300e /hw/pci_host.h
parent0f4f039b9895e2e52d591a123017cb53fe636f9d (diff)
pci-host: Delegate bswap to mmio layer
The only reason we have bswap versions of the pci host code is that most pci host devices are little endian. The ppc e500 is the only odd one here, being big endian. So let's directly pass the endianness down to the mmio layer and not worry about it on the pci host layer. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/pci_host.h')
-rw-r--r--hw/pci_host.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/hw/pci_host.h b/hw/pci_host.h
index bd8ede8b72..0a585951e0 100644
--- a/hw/pci_host.h
+++ b/hw/pci_host.h
@@ -33,9 +33,7 @@
struct PCIHostState {
SysBusDevice busdev;
- ReadWriteHandler conf_noswap_handler;
ReadWriteHandler conf_handler;
- ReadWriteHandler data_noswap_handler;
ReadWriteHandler data_handler;
uint32_t config_reg;
PCIBus *bus;
@@ -45,8 +43,8 @@ void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
/* for mmio */
-int pci_host_conf_register_mmio(PCIHostState *s, int swap);
-int pci_host_data_register_mmio(PCIHostState *s, int swap);
+int pci_host_conf_register_mmio(PCIHostState *s, int endian);
+int pci_host_data_register_mmio(PCIHostState *s, int endian);
/* for ioio */
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);