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authorMichael S. Tsirkin <mst@redhat.com>2013-03-04 11:23:49 +0200
committerMichael S. Tsirkin <mst@redhat.com>2013-03-26 21:02:17 +0200
commit45eb768c706d3a5fbe55224c589e8b4e252781d9 (patch)
treed3de1d700976fe8efae8942b64f66d4626137f2b /hw/pci/pcie_port.c
parentba7d8515c1e929baccea9f53d06d131fd2b007a1 (diff)
pci_bridge: factor out common code
Reuse common code in pcie_port, override the hardwired-to-0 bits per PCI Express spec. No functional change but makes the code easier to follow. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci/pcie_port.c')
-rw-r--r--hw/pci/pcie_port.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
index 1be107b0c9..91b53a0fc2 100644
--- a/hw/pci/pcie_port.c
+++ b/hw/pci/pcie_port.c
@@ -27,15 +27,17 @@ void pcie_port_init_reg(PCIDevice *d)
pci_set_word(d->config + PCI_STATUS, 0);
pci_set_word(d->config + PCI_SEC_STATUS, 0);
- /* Unlike conventional pci bridge, some bits are hardwired to 0. */
-#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
- pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
- PCI_BRIDGE_CTL_PARITY |
- PCI_BRIDGE_CTL_ISA |
- PCI_BRIDGE_CTL_VGA |
- PCI_BRIDGE_CTL_VGA_16BIT | /* Req, but no alias support yet */
- PCI_BRIDGE_CTL_SERR |
- PCI_BRIDGE_CTL_BUS_RESET);
+ /*
+ * Unlike conventional pci bridge, for some bits the spec states:
+ * Does not apply to PCI Express and must be hardwired to 0.
+ */
+ pci_word_test_and_clear_mask(d->wmask + PCI_BRIDGE_CONTROL,
+ PCI_BRIDGE_CTL_MASTER_ABORT |
+ PCI_BRIDGE_CTL_FAST_BACK |
+ PCI_BRIDGE_CTL_DISCARD |
+ PCI_BRIDGE_CTL_SEC_DISCARD |
+ PCI_BRIDGE_CTL_DISCARD_STATUS |
+ PCI_BRIDGE_CTL_DISCARD_SERR);
}
/**************************************************************************