aboutsummaryrefslogtreecommitdiff
path: root/hw/arm/nrf51_soc.c
diff options
context:
space:
mode:
authorJoel Stanley <joel@jms.id.au>2018-09-25 14:02:31 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-09-25 14:14:07 +0100
commit673b2d42a8bfbc36bbfd9aad18410b3970913043 (patch)
tree10cb23fc06a6525c0b2c3a3a95588ccdb6b15e51 /hw/arm/nrf51_soc.c
parentc0066d1a1900e8f44a004c588257116c25bbde55 (diff)
downloadqemu-arm-673b2d42a8bfbc36bbfd9aad18410b3970913043.tar.gz
arm: Add Nordic Semiconductor nRF51 SoC
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/nrf51_soc.c')
-rw-r--r--hw/arm/nrf51_soc.c133
1 files changed, 133 insertions, 0 deletions
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
new file mode 100644
index 0000000000..1a59ef4552
--- /dev/null
+++ b/hw/arm/nrf51_soc.c
@@ -0,0 +1,133 @@
+/*
+ * Nordic Semiconductor nRF51 SoC
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
+ *
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "hw/sysbus.h"
+#include "hw/boards.h"
+#include "hw/devices.h"
+#include "hw/misc/unimp.h"
+#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+#include "cpu.h"
+
+#include "hw/arm/nrf51_soc.h"
+
+#define IOMEM_BASE 0x40000000
+#define IOMEM_SIZE 0x20000000
+
+#define FICR_BASE 0x10000000
+#define FICR_SIZE 0x000000fc
+
+#define FLASH_BASE 0x00000000
+#define SRAM_BASE 0x20000000
+
+#define PRIVATE_BASE 0xF0000000
+#define PRIVATE_SIZE 0x10000000
+
+/*
+ * The size and base is for the NRF51822 part. If other parts
+ * are supported in the future, add a sub-class of NRF51SoC for
+ * the specific variants
+ */
+#define NRF51822_FLASH_SIZE (256 * 1024)
+#define NRF51822_SRAM_SIZE (16 * 1024)
+
+static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ NRF51State *s = NRF51_SOC(dev_soc);
+ Error *err = NULL;
+
+ if (!s->board_memory) {
+ error_setg(errp, "memory property was not set");
+ return;
+ }
+
+ object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
+
+ memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size,
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);
+
+ memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
+
+ create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
+ create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
+ create_unimplemented_device("nrf51_soc.private",
+ PRIVATE_BASE, PRIVATE_SIZE);
+}
+
+static void nrf51_soc_init(Object *obj)
+{
+ NRF51State *s = NRF51_SOC(obj);
+
+ memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
+
+ sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
+ TYPE_ARMV7M);
+ qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
+ ARM_CPU_TYPE_NAME("cortex-m0"));
+ qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
+}
+
+static Property nrf51_soc_properties[] = {
+ DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
+ DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
+ NRF51822_FLASH_SIZE),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void nrf51_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = nrf51_soc_realize;
+ dc->props = nrf51_soc_properties;
+}
+
+static const TypeInfo nrf51_soc_info = {
+ .name = TYPE_NRF51_SOC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NRF51State),
+ .instance_init = nrf51_soc_init,
+ .class_init = nrf51_soc_class_init,
+};
+
+static void nrf51_soc_types(void)
+{
+ type_register_static(&nrf51_soc_info);
+}
+type_init(nrf51_soc_types)