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authorArtyom Tarasenko <atar4qemu@gmail.com>2012-05-12 11:15:23 +0200
committerBlue Swirl <blauwirbel@gmail.com>2012-05-12 09:49:19 +0000
commit94d1991445fa3582c042ee4e5b72606e2fc39cc2 (patch)
treee21812c9124b06547351537926a26c1495bc14d7 /hw/apb_pci.c
parentd1d80055baddf2c107d9da893f79c9199362e2e9 (diff)
sun4u: implement interrupt clearing registers
Implement registers for clearing OBIO and PCI interrupts Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/apb_pci.c')
-rw-r--r--hw/apb_pci.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index d4e11bc1bb..c28411a460 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -85,6 +85,8 @@ typedef struct APBState {
unsigned int nr_resets;
} APBState;
+static void pci_apb_set_irq(void *opaque, int irq_num, int level);
+
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
@@ -113,6 +115,16 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
}
break;
+ case 0x1400 ... 0x143f: /* PCI interrupt clear */
+ if (addr & 4) {
+ pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
+ }
+ break;
+ case 0x1800 ... 0x1860: /* OBIO interrupt clear */
+ if (addr & 4) {
+ pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
+ }
+ break;
case 0x2000 ... 0x202f: /* PCI control */
s->pci_control[(addr & 0x3f) >> 2] = val;
break;