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authorPeter Maydell <peter.maydell@linaro.org>2018-12-14 13:30:48 +0000
committerPeter Maydell <peter.maydell@linaro.org>2018-12-14 13:30:48 +0000
commit3c8133f973767460f8e42c9e656f2f3ed703d00d (patch)
treec4c81c69036ee9f15608d4b4cf3ae035a269b09c /exec.c
parent75693e14113c0d1c1ebc1e8405e00879d2a11c84 (diff)
Rename cpu_physical_memory_write_rom() to address_space_write_rom()
The API of cpu_physical_memory_write_rom() is odd, because it takes an AddressSpace, unlike all the other cpu_physical_memory_* access functions. Rename it to address_space_write_rom(), and bring its API into line with address_space_write(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20181122133507.30950-3-peter.maydell@linaro.org
Diffstat (limited to 'exec.c')
-rw-r--r--exec.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/exec.c b/exec.c
index 92679508ba..6e875f0640 100644
--- a/exec.c
+++ b/exec.c
@@ -3430,11 +3430,12 @@ static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
- const uint8_t *buf, int len)
+MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
+ MemTxAttrs attrs,
+ const uint8_t *buf, int len)
{
- address_space_write_rom_internal(as, addr, MEMTXATTRS_UNSPECIFIED,
- buf, len, WRITE_DATA);
+ return address_space_write_rom_internal(as, addr, attrs,
+ buf, len, WRITE_DATA);
}
void cpu_flush_icache_range(hwaddr start, int len)
@@ -3879,8 +3880,9 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write) {
- cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
- phys_addr, buf, l);
+ address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
+ MEMTXATTRS_UNSPECIFIED,
+ buf, l);
} else {
address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
MEMTXATTRS_UNSPECIFIED,