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authorPeter Collingbourne <pcc@google.com>2021-06-16 12:56:14 -0700
committerPeter Maydell <peter.maydell@linaro.org>2021-06-21 17:12:52 +0100
commit80fd1f22fc3a95b69b5b25d47c9727e7659da2ff (patch)
treeabdf5aae6ca448686e05120bf98ab5fb7edfb9e7 /docs/system/arm/emulation.rst
parentd93a468d1302f29afcb1e368fb39da3fe024fc39 (diff)
downloadqemu-arm-80fd1f22fc3a95b69b5b25d47c9727e7659da2ff.tar.gz
target/arm: Implement MTE3
MTE3 introduces an asymmetric tag checking mode, in which loads are checked synchronously and stores are checked asynchronously. Add support for it. Signed-off-by: Peter Collingbourne <pcc@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210616195614.11785-1-pcc@google.com [PMM: Add line to emulation.rst] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 836c1ca845..144dc491d9 100644
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+++ b/docs/system/arm/emulation.rst
@@ -29,6 +29,7 @@ the following architecture extensions:
- FEAT_LSE (Large System Extensions)
- FEAT_MTE (Memory Tagging Extension)
- FEAT_MTE2 (Memory Tagging Extension)
+- FEAT_MTE3 (MTE Asymmetric Fault Handling)
- FEAT_PAN (Privileged access never)
- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
- FEAT_PAuth (Pointer authentication)