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authorYongbok Kim <yongbok.kim@imgtec.com>2014-06-27 08:49:05 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2014-10-13 12:38:25 +0100
commit15eacb9b525ad7f6b9326eeb8eeb151721d66570 (patch)
tree1ab333d0bb613ff37474b5ffe001b6ae67937e13 /disas
parent01f72885794124f94b24d97daf3c8630424cfd79 (diff)
downloadqemu-arm-15eacb9b525ad7f6b9326eeb8eeb151721d66570.tar.gz
target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'disas')
-rw-r--r--disas/mips.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/disas/mips.c b/disas/mips.c
index 8ee8758e50..61313f494c 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -1246,6 +1246,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6},
{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
+{"align", "d,v,t", 0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6},
+{"dalign", "d,v,t", 0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t, 0, I64R6},
+{"bitswap", "d,w", 0x7c000020, 0xffe007ff, WR_d|RD_t, 0, I32R6},
+{"dbitswap","d,w", 0x7c000024, 0xffe007ff, WR_d|RD_t, 0, I64R6},
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */