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authorRichard Henderson <rth@twiddle.net>2014-08-06 11:48:48 -0700
committerRichard Henderson <rth@redhat.com>2014-09-29 14:55:27 -0400
commit90379ca84ebe94b0adc08794d90ea1e196b2a724 (patch)
treec55ace94c6a479b4ecf8f01042553d5712aaa93c /disas/sparc.c
parent609ac1e16473e7dfc4dc54becde4b1902dbdf919 (diff)
tcg-sparc: Use ADDXC in addsub2_i64
On T4 and newer Sparc chips we have an add-with-carry insn that takes its input from %xcc instead of %icc. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'disas/sparc.c')
-rw-r--r--disas/sparc.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/disas/sparc.c b/disas/sparc.c
index 8eb22e6fc3..092e1b6098 100644
--- a/disas/sparc.c
+++ b/disas/sparc.c
@@ -2042,6 +2042,9 @@ IMPDEP ("impdep2", 0x37),
#undef IMPDEP
+{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, v9b },
+{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, v9b },
+
};
static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));