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authorRichard Henderson <rth@twiddle.net>2012-09-21 10:34:21 -0700
committerRichard Henderson <rth@twiddle.net>2012-09-21 22:02:16 +0200
commit9b9c37c36439ee0452632253dac7a31897f27f70 (patch)
treeb5c8fa6937fcc7a4d2f75cd64051f66d6bbfc25b /disas.c
parentd5dd696fe3049657c08eb14f40cb74b6e94e79cc (diff)
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Current code doesn't actually work in 32-bit mode at all. Since no one really noticed, drop the complication of v7 and v8 cpus. Eliminate the --sparc_cpu configure option and standardize macro testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'disas.c')
-rw-r--r--disas.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/disas.c b/disas.c
index 7b2acc9943..b801c8f51d 100644
--- a/disas.c
+++ b/disas.c
@@ -316,9 +316,7 @@ void disas(FILE *out, void *code, unsigned long size)
print_insn = print_insn_alpha;
#elif defined(__sparc__)
print_insn = print_insn_sparc;
-#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
disasm_info.mach = bfd_mach_sparc_v9b;
-#endif
#elif defined(__arm__)
print_insn = print_insn_arm;
#elif defined(__MIPSEB__)