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authorAndreas Färber <afaerber@suse.de>2013-09-01 17:52:07 +0200
committerAndreas Färber <afaerber@suse.de>2014-03-13 19:20:48 +0100
commit611d4f996f650294483ff4b01c3140651e2dd29c (patch)
tree94808c5ae0adabd499b28f734d33db2a5fe5452b /cputlb.c
parent648f034c6cd81c64d93a1cfd7bb262006f560649 (diff)
translate-all: Change tb_flush_jmp_cache() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'cputlb.c')
-rw-r--r--cputlb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cputlb.c b/cputlb.c
index 0eb1801cc2..6b2cdb201a 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -106,7 +106,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr)
tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
}
- tb_flush_jmp_cache(env, addr);
+ tb_flush_jmp_cache(cpu, addr);
}
/* update the TLBs so that writes to code in the virtual page 'addr'