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authorPaul Brook <paul@codesourcery.com>2010-03-17 02:14:28 +0000
committerPaul Brook <paul@codesourcery.com>2010-03-17 02:44:41 +0000
commitd4c430a80f000d722bb70287af4d4c184a8d7006 (patch)
tree9b9d059b2158f25fc0629fddcef192e3d791b187 /cpu-defs.h
parent409dbce54b57b85bd229174da86d77ca08508508 (diff)
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'cpu-defs.h')
-rw-r--r--cpu-defs.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/cpu-defs.h b/cpu-defs.h
index 47c1d85968..2e94585ae1 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -111,6 +111,8 @@ typedef struct CPUTLBEntry {
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
+ target_ulong tlb_flush_addr; \
+ target_ulong tlb_flush_mask;
#else