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authorAurelien Jarno <aurelien@aurel32.net>2009-10-17 14:17:47 +0200
committerAurelien Jarno <aurelien@aurel32.net>2009-12-01 00:06:15 +0000
commitafa05235a5860e7e2153b428294bd44569d4039b (patch)
treec14d786d67390068c87e82ddf3e82a821f05579b /configure
parente7139c440c489ed31bb81ccb5e456ae9d8fe1c1e (diff)
tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> A few words about design choices: * Two registers, at and t0, are reserved for TCG internal use. They are useful for bswap and 64-bit ops. * Most ops supports a constant argument with value 0, which is actually mapped to the zero register. * While the at register is available for constant loading, ops only support a limited range of constants. TCG does a better job doing the register allocation and constant loading by itself. There are plenty of registers available anyway. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'configure')
-rwxr-xr-xconfigure7
1 files changed, 6 insertions, 1 deletions
diff --git a/configure b/configure
index c50aa874c0..dca5a430f6 100755
--- a/configure
+++ b/configure
@@ -134,13 +134,15 @@ elif check_define _ARCH_PPC ; then
else
cpu="ppc"
fi
+elif check_define __mips__ ; then
+ cpu="mips"
else
cpu=`uname -m`
fi
target_list=""
case "$cpu" in
- alpha|cris|ia64|m68k|microblaze|mips|mips64|ppc|ppc64|sparc64)
+ alpha|cris|ia64|m68k|microblaze|ppc|ppc64|sparc64)
cpu="$cpu"
;;
i386|i486|i586|i686|i86pc|BePC)
@@ -158,6 +160,9 @@ case "$cpu" in
parisc|parisc64)
cpu="hppa"
;;
+ mips*)
+ cpu="mips"
+ ;;
s390*)
cpu="s390"
;;