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authorPeter Maydell <peter.maydell@linaro.org>2016-01-14 12:54:41 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-01-14 12:54:41 +0000
commitbd9c5b33acc2a54845148545f81fb485fe68a584 (patch)
treebc7160326d866b4cc35e684423c966d939cdba2d
parent8154c4c17f332383d68f2be8ef03f3764cb09cf2 (diff)
downloadqemu-arm-bd9c5b33acc2a54845148545f81fb485fe68a584.tar.gz
HACK: rearrange the virt memory map to suit OP-TEEmulti-ases
The current OP-TEE codebase expects the secure UART to be at 0x09010000 and irq 2 (it is based on an old non-upstream patch to add a second uart, and upstream used that memory map area for something else). When the TZ support is upstream in QEMU we can move OP-TEE on to a proper upstream QEMU and update it to use the new UART location, but for now this hack patch allows running a more-or-less unmodified OP-TEE. Put the secure UART at the address and irq where OP-TEE expects it, moving some other devices down to make space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--hw/arm/virt.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e0ca2315a9..1e0e0cf5f5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -119,10 +119,10 @@ static const MemMapEntry a15memmap[] = {
/* This redistributor space allows up to 2*64kB*123 CPUs */
[VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
[VIRT_UART] = { 0x09000000, 0x00001000 },
- [VIRT_RTC] = { 0x09010000, 0x00001000 },
+ [VIRT_RTC] = { 0x09040000, 0x00001000 },
[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
[VIRT_GPIO] = { 0x09030000, 0x00001000 },
- [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
+ [VIRT_SECURE_UART] = { 0x09010000, 0x00001000 },
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
@@ -136,10 +136,10 @@ static const MemMapEntry a15memmap[] = {
static const int a15irqmap[] = {
[VIRT_UART] = 1,
- [VIRT_RTC] = 2,
+ [VIRT_RTC] = 8,
[VIRT_PCIE] = 3, /* ... to 6 */
[VIRT_GPIO] = 7,
- [VIRT_SECURE_UART] = 8,
+ [VIRT_SECURE_UART] = 2,
[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */