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authorLiu, Jinsong <jinsong.liu@intel.com>2014-03-03 05:24:14 +0000
committerPaolo Bonzini <pbonzini@redhat.com>2014-03-11 11:49:00 +0100
commitb0f15a5d5628994c71a6f428f360a5a537ad3b39 (patch)
treef6a914fc333f6d8d49dd0e2ecfcb16392e7ea065
parentf9a49dfa0202348b543983d61fab441b7374a874 (diff)
downloadqemu-arm-b0f15a5d5628994c71a6f428f360a5a537ad3b39.tar.gz
target-i386: bugfix of Intel MPX
The correct size of cpuid 0x0d sub-leaf 4 is 0x40, not 0x10. This is confirmed by Anvin H Peter and Mallick Asit K. Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Asit K Mallick <asit.k.mallick@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
-rw-r--r--target-i386/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 0e8812a11d..9f69d7e192 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -339,7 +339,7 @@ static const ExtSaveArea ext_save_areas[] = {
[3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
.offset = 0x3c0, .size = 0x40 },
[4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
- .offset = 0x400, .size = 0x10 },
+ .offset = 0x400, .size = 0x40 },
};
const char *get_register_name_32(unsigned int reg)