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authorJohn Snow <jsnow@redhat.com>2016-09-29 14:46:15 -0400
committerJohn Snow <jsnow@redhat.com>2016-09-29 14:46:15 -0400
commit9da82227caa74fb6fbea224dad91fe5b7cc115a5 (patch)
tree72e9cb4ad0492255431654354c434db8290dbaf8
parentc640f2849ee8775fe1bbd7a2772610aa77816f9f (diff)
downloadqemu-arm-9da82227caa74fb6fbea224dad91fe5b7cc115a5.tar.gz
ide: fix DMA register transitions
ATA8-APT defines the state transitions for both a host controller and for the hardware device during the lifecycle of a DMA transfer, in section 9.7 "DMA command protocol." One of the interesting tidbits here is that when a device transitions from DDMA0 ("Prepare state") to DDMA1 ("Data_Transfer State"), it can choose to set either BSY or DRQ to signal this transition, but not both. as ide_sector_dma_start is the last point in our preparation process before we begin the real data transfer process (for either AHCI or BMDMA), this is the correct transition point for DDMA0 to DDMA1. I have chosen !BSY && DRQ for QEMU to make the transition from DDMA0 the most obvious. Reported-by: Benjamin David Lunt <fys@fysnet.net> Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Tested-by: Stefan Weil <sw@weilnetz.de> Message-id: 1470175541-19344-1-git-send-email-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
-rw-r--r--hw/ide/core.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ide/core.c b/hw/ide/core.c
index b0e42a6562..1bee18d86e 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -908,7 +908,7 @@ eot:
static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
{
- s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
+ s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
s->io_buffer_size = 0;
s->dma_cmd = dma_cmd;