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authorLluís Vilanova <vilanova@ac.upc.edu>2016-06-09 19:31:41 +0200
committerStefan Hajnoczi <stefanha@redhat.com>2016-06-20 15:30:01 +0100
commit7c2550432abe62f53e6df878ceba6ceaf71f0e7e (patch)
treed9560c139a0e59672cc44578cec766dd45e64370
parent5edbd4e30426d3a0d712510b2509a521e35192b1 (diff)
downloadqemu-arm-7c2550432abe62f53e6df878ceba6ceaf71f0e7e.tar.gz
exec: [tcg] Track which vCPU is performing translation and execution
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
-rw-r--r--target-alpha/translate.c1
-rw-r--r--target-arm/translate.c1
-rw-r--r--target-cris/translate.c1
-rw-r--r--target-cris/translate_v10.c1
-rw-r--r--target-i386/translate.c1
-rw-r--r--target-lm32/translate.c1
-rw-r--r--target-m68k/translate.c1
-rw-r--r--target-microblaze/translate.c1
-rw-r--r--target-mips/translate.c1
-rw-r--r--target-moxie/translate.c1
-rw-r--r--target-openrisc/translate.c1
-rw-r--r--target-ppc/translate.c1
-rw-r--r--target-s390x/translate.c1
-rw-r--r--target-sh4/translate.c1
-rw-r--r--target-sparc/translate.c1
-rw-r--r--target-tilegx/translate.c1
-rw-r--r--target-tricore/translate.c1
-rw-r--r--target-unicore32/translate.c1
-rw-r--r--target-xtensa/translate.c1
-rw-r--r--tcg/tcg.h4
-rw-r--r--translate-all.c2
21 files changed, 25 insertions, 0 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index f9b2426636..243567b8fc 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -151,6 +151,7 @@ void alpha_translate_init(void)
done_init = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 3e7146769d..bd5d5cb576 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -85,6 +85,7 @@ void arm_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-cris/translate.c b/target-cris/translate.c
index cc515690e1..f4a8d7d000 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3374,6 +3374,7 @@ void cris_initialize_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 06ba1ef86a..4707a18e77 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1250,6 +1250,7 @@ void cris_initialize_crisv10_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-i386/translate.c b/target-i386/translate.c
index f010022fcd..7dea18bd63 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8152,6 +8152,7 @@ void tcg_x86_init(void)
initialized = true;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUX86State, cc_op), "cc_op");
cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 526b4374e6..2d8caebbfc 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1202,6 +1202,7 @@ void lm32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 83db42a7d3..ecd5e5c8fd 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -78,6 +78,7 @@ void m68k_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
#define DEFO32(name, offset) \
QREG_##name = tcg_global_mem_new_i32(cpu_env, \
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index c54304aca5..80098ece15 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1878,6 +1878,7 @@ void mb_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
env_debug = tcg_global_mem_new(cpu_env,
offsetof(CPUMBState, debug),
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f420680d1f..aaa1d02683 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20005,6 +20005,7 @@ void mips_tcg_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index 58200c25d3..0660b44c08 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -106,6 +106,7 @@ void moxie_translate_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMoxieState, pc), "$pc");
for (i = 0; i < 16; i++)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index c08876b14a..28c944657c 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -78,6 +78,7 @@ void openrisc_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
env_flags = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 30dc76aafa..df4e0a308b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -88,6 +88,7 @@ void ppc_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
p = cpu_reg_names;
cpu_reg_names_size = sizeof(cpu_reg_names);
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index ce5db5dd46..3c3487a5a9 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -169,6 +169,7 @@ void s390x_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
psw_addr = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUS390XState, psw.addr),
"psw_addr");
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 7518eb5508..ca80cf70ca 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -101,6 +101,7 @@ void sh4_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 24; i++)
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index afd306fbab..afd46b878f 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5404,6 +5404,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
inited = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
offsetof(CPUSPARCState, regwptr),
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index bdea673e5b..11c9732389 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2443,6 +2443,7 @@ void tilegx_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index eb3deac889..9a50df9a88 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8835,6 +8835,7 @@ void tricore_tcg_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
/* reg init */
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index c4d45fa0f4..09354f92d2 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -70,6 +70,7 @@ void uc32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 2a8e5c5d94..4c1e48748b 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -219,6 +219,7 @@ void xtensa_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, pc), "pc");
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 909db3fc02..66d7fc01c5 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -599,6 +599,10 @@ struct TCGContext {
TBContext tb_ctx;
+ /* Track which vCPU triggers events */
+ CPUState *cpu; /* *_trans */
+ TCGv_env tcg_env; /* *_exec */
+
/* The TCGBackendData structure is private to tcg-target.inc.c. */
struct TCGBackendData *be;
diff --git a/translate-all.c b/translate-all.c
index 3f402dfe04..eaa95e4cd7 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1182,7 +1182,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(&tcg_ctx);
+ tcg_ctx.cpu = ENV_GET_CPU(env);
gen_intermediate_code(env, tb);
+ tcg_ctx.cpu = NULL;
trace_translate_block(tb, tb->pc, tb->tc_ptr);