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authorAlistair Francis <alistair.francis@xilinx.com>2015-06-18 21:16:29 -0700
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2015-06-21 17:20:15 +1000
commit714461237083c1eadcb9d686f8ce4088737c1d0a (patch)
tree66599bcbe83d070ee1ee6d15e1278960bdf64bf3
parentbe67e9ab9740d5a80e5c37bfd35247a4e449bc5a (diff)
downloadqemu-arm-714461237083c1eadcb9d686f8ce4088737c1d0a.tar.gz
target-microblaze: Convert use-mmu to a CPU property
Originally the use-mmu PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--target-microblaze/cpu-qom.h1
-rw-r--r--target-microblaze/cpu.c5
-rw-r--r--target-microblaze/cpu.h2
-rw-r--r--target-microblaze/helper.c2
4 files changed, 6 insertions, 4 deletions
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index aa9c0325cf..6bde2e9fc2 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -64,6 +64,7 @@ typedef struct MicroBlazeCPU {
bool stackprot;
uint32_t base_vectors;
uint8_t use_fpu;
+ bool use_mmu;
} cfg;
CPUMBState env;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index a6b6fd7ac8..c4cd68ab79 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -98,7 +98,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| PVR0_USE_EXC_MASK \
| PVR0_USE_ICACHE_MASK \
| PVR0_USE_DCACHE_MASK \
- | PVR0_USE_MMU \
| (0xb << 8);
env->pvr.regs[2] = PVR2_D_OPB_MASK \
| PVR2_D_LMB_MASK \
@@ -114,7 +113,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
| 0;
env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
- (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
+ (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
+ (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
@@ -168,6 +168,7 @@ static Property mb_properties[] = {
* are enabled
*/
DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
+ DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 60a7500b80..54e41e8721 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -122,7 +122,7 @@ typedef struct CPUMBState CPUMBState;
#define PVR0_USE_EXC_MASK 0x04000000
#define PVR0_USE_ICACHE_MASK 0x02000000
#define PVR0_USE_DCACHE_MASK 0x01000000
-#define PVR0_USE_MMU 0x00800000 /* new */
+#define PVR0_USE_MMU_MASK 0x00800000
#define PVR0_USE_BTC 0x00400000
#define PVR0_ENDI 0x00200000
#define PVR0_FAULT 0x00100000
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 69c3252554..5156c12dc6 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -56,7 +56,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int prot;
mmu_available = 0;
- if (env->pvr.regs[0] & PVR0_USE_MMU) {
+ if (cpu->cfg.use_mmu) {
mmu_available = 1;
if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {