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authorAlexander Graf <agraf@suse.de>2013-09-03 20:12:04 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-09-10 19:11:28 +0100
commit3407ad0e7a6f04905fc6a8ea72be03553e777988 (patch)
treea8a46a001768bb46fec91ae55b4350289af1eef4
parentf570c61e694d78fc2f6717f4fbb7e820bf72d8dc (diff)
downloadqemu-arm-3407ad0e7a6f04905fc6a8ea72be03553e777988.tar.gz
target-arm: Export cpu_env
The cpu_env tcg variable will be used by both the AArch32 and AArch64 handling code. Unstaticify it, so that both sides can make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-5-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate.c2
-rw-r--r--target-arm/translate.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 450a0b6d28..2605833685 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -61,7 +61,7 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
#define DISAS_WFI 4
#define DISAS_SWI 5
-static TCGv_ptr cpu_env;
+TCGv_ptr cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];
diff --git a/target-arm/translate.h b/target-arm/translate.h
index e727bc66fe..8ba14339a9 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -24,4 +24,6 @@ typedef struct DisasContext {
int vec_stride;
} DisasContext;
+extern TCGv_ptr cpu_env;
+
#endif /* TARGET_ARM_TRANSLATE_H */