aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2019-11-15 11:22:33 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-11-15 11:22:33 +0000
commit19bef037fe096b17edda103fd513ce6451da23c8 (patch)
treebc097d63bbc7de8d381198742e99443c32743612
parente10bf1fe00eceb2dbff973f5939036ef3f3c77a4 (diff)
parent6911fde41006b2afe3510755c4cff259ca56c1d9 (diff)
downloadqemu-arm-19bef037fe096b17edda103fd513ce6451da23c8.tar.gz
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc2' into staging
RISC-V Fixes for 4.2-rc2 This contains a handful of patches that I'd like to target for 4.2: * OpenSBI upgrade to 0.5 * Increase in the flash size of the virt board. * A non-functional cleanup. * A cleanup to our MIP handling that avoids atomics. This passes "make check" and boots OpenEmbedded for me. # gpg: Signature made Thu 14 Nov 2019 18:39:27 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.2-rc2: riscv/virt: Increase flash size opensbi: Upgrade from v0.4 to v0.5 target/riscv: Remove atomic accesses to MIP CSR remove unnecessary ifdef TARGET_RISCV64 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/riscv/virt.c2
-rw-r--r--pc-bios/opensbi-riscv32-virt-fw_jump.binbin36888 -> 40984 bytes
-rw-r--r--pc-bios/opensbi-riscv64-sifive_u-fw_jump.binbin45064 -> 49160 bytes
-rw-r--r--pc-bios/opensbi-riscv64-virt-fw_jump.binbin40968 -> 45064 bytes
m---------roms/opensbi0
-rw-r--r--target/riscv/cpu.c5
-rw-r--r--target/riscv/cpu.h9
-rw-r--r--target/riscv/cpu_helper.c48
-rw-r--r--target/riscv/csr.c2
-rw-r--r--target/riscv/translate.c4
10 files changed, 23 insertions, 47 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cc8f311e6b..23f340df19 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -62,7 +62,7 @@ static const struct MemmapEntry {
[VIRT_PLIC] = { 0xc000000, 0x4000000 },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
- [VIRT_FLASH] = { 0x20000000, 0x2000000 },
+ [VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
[VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin
index f5bcaa5695..6c5b7b89f6 100644
--- a/pc-bios/opensbi-riscv32-virt-fw_jump.bin
+++ b/pc-bios/opensbi-riscv32-virt-fw_jump.bin
Binary files differ
diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
index eb22aefdfb..971f2be405 100644
--- a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
+++ b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
Binary files differ
diff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin b/pc-bios/opensbi-riscv64-virt-fw_jump.bin
index 4cec6f0210..45a5aed1ce 100644
--- a/pc-bios/opensbi-riscv64-virt-fw_jump.bin
+++ b/pc-bios/opensbi-riscv64-virt-fw_jump.bin
Binary files differ
diff --git a/roms/opensbi b/roms/opensbi
-Subproject ce228ee0919deb9957192d723eecc8aaae2697c
+Subproject be92da280d87c38a2e0adc5d3f43bab7b5468f0
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3939963b71..d37861a430 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -224,8 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ",
- (target_ulong)atomic_read(&env->mip));
+ qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
@@ -275,7 +274,7 @@ static bool riscv_cpu_has_work(CPUState *cs)
* Definition of the WFI instruction requires it to ignore the privilege
* mode and delegation registers, but respect individual enables
*/
- return (atomic_read(&env->mip) & env->mie) != 0;
+ return (env->mip & env->mie) != 0;
#else
return true;
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8c64c68538..e59343e13c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -121,15 +121,6 @@ struct CPURISCVState {
target_ulong mhartid;
target_ulong mstatus;
- /*
- * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
- * by I/O threads. It should be read with atomic_read. It should be updated
- * using riscv_cpu_update_mip with the iothread mutex held. The iothread
- * mutex must be held because mip must be consistent with the CPU inturrept
- * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
- * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
- * mip is 32-bits to allow atomic_read on 32-bit hosts.
- */
uint32_t mip;
uint32_t miclaim;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f13131a51b..767c8762ac 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
@@ -38,7 +39,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
- target_ulong pending = atomic_read(&env->mip) & env->mie;
+ target_ulong pending = env->mip & env->mie;
target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie);
target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie);
target_ulong irqs = (pending & ~env->mideleg & -mie) |
@@ -92,42 +93,29 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
}
}
-struct CpuAsyncInfo {
- uint32_t new_mip;
-};
-
-static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state,
- run_on_cpu_data data)
-{
- struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr;
-
- if (info->new_mip) {
- cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD);
- } else {
- cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD);
- }
-
- g_free(info);
-}
-
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
- struct CpuAsyncInfo *info;
- uint32_t old, new, cmp = atomic_read(&env->mip);
+ uint32_t old = env->mip;
+ bool locked = false;
+
+ if (!qemu_mutex_iothread_locked()) {
+ locked = true;
+ qemu_mutex_lock_iothread();
+ }
- do {
- old = cmp;
- new = (old & ~mask) | (value & mask);
- cmp = atomic_cmpxchg(&env->mip, old, new);
- } while (old != cmp);
+ env->mip = (env->mip & ~mask) | (value & mask);
- info = g_new(struct CpuAsyncInfo, 1);
- info->new_mip = new;
+ if (env->mip) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
- async_run_on_cpu(cs, riscv_cpu_update_mip_irqs_async,
- RUN_ON_CPU_HOST_PTR(info));
+ if (locked) {
+ qemu_mutex_unlock_iothread();
+ }
return old;
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 974c9c20b5..da02f9f0b1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -579,7 +579,7 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
if (mask) {
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
} else {
- old_mip = atomic_read(&env->mip);
+ old_mip = env->mip;
}
if (ret_value) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b26533d4fd..ab6a891dc3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -64,12 +64,10 @@ static const int tcg_memop_lookup[8] = {
[0] = MO_SB,
[1] = MO_TESW,
[2] = MO_TESL,
+ [3] = MO_TEQ,
[4] = MO_UB,
[5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
[6] = MO_TEUL,
-#endif
};
#endif