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authorAndreas Färber <afaerber@suse.de>2013-09-03 13:59:37 +0200
committerAndreas Färber <afaerber@suse.de>2014-03-13 19:52:47 +0100
commit0c591eb0a9d0593d71d7cb61f4184222ac14fdd2 (patch)
tree27fc876065b6ed65266b3615a424e6e2cafdfd30
parent00c8cb0a36f51a6866a83c08962d12a0eb21864b (diff)
downloadqemu-arm-0c591eb0a9d0593d71d7cb61f4184222ac14fdd2.tar.gz
cputlb: Change tlb_set_page() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
-rw-r--r--cputlb.c4
-rw-r--r--include/exec/exec-all.h2
-rw-r--r--target-alpha/helper.c2
-rw-r--r--target-arm/helper.c2
-rw-r--r--target-cris/helper.c2
-rw-r--r--target-i386/helper.c2
-rw-r--r--target-lm32/helper.c6
-rw-r--r--target-m68k/helper.c3
-rw-r--r--target-microblaze/helper.c4
-rw-r--r--target-mips/helper.c2
-rw-r--r--target-moxie/helper.c2
-rw-r--r--target-openrisc/mmu.c2
-rw-r--r--target-ppc/mmu-hash32.c8
-rw-r--r--target-ppc/mmu-hash64.c4
-rw-r--r--target-ppc/mmu_helper.c2
-rw-r--r--target-s390x/helper.c2
-rw-r--r--target-sh4/helper.c2
-rw-r--r--target-sparc/mmu_helper.c6
-rw-r--r--target-unicore32/softmmu.c2
-rw-r--r--target-xtensa/op_helper.c8
20 files changed, 33 insertions, 34 deletions
diff --git a/cputlb.c b/cputlb.c
index b280e81c6f..7bd3573025 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -221,10 +221,11 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
/* Add a new TLB entry. At most one entry for a given virtual address
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
+ CPUArchState *env = cpu->env_ptr;
MemoryRegionSection *section;
unsigned int index;
target_ulong address;
@@ -232,7 +233,6 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
uintptr_t addend;
CPUTLBEntry *te;
hwaddr iotlb, xlat, sz;
- CPUState *cpu = ENV_GET_CPU(env);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 4cc11bb652..502b7aa084 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -100,7 +100,7 @@ void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
/* cputlb.c */
void tlb_flush_page(CPUState *cpu, target_ulong addr);
void tlb_flush(CPUState *cpu, int flush_global);
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index fdb033564c..cbd03c415b 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -345,7 +345,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
return 1;
}
- tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
+ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a9db2796c5..aa5f22d14f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3676,7 +3676,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
/* Map a single [sub]page. */
phys_addr &= ~(hwaddr)0x3ff;
address &= ~(uint32_t)0x3ff;
- tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
diff --git a/target-cris/helper.c b/target-cris/helper.c
index ec84b57c0b..4092d279ba 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
*/
phy = res.phy & ~0x80000000;
prot = res.prot;
- tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 54899a0542..4f447b8cf9 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -877,7 +877,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
paddr = (pte & TARGET_PAGE_MASK) + page_offset;
vaddr = virt_addr + page_offset;
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
do_fault_protect:
error_code = PG_ERROR_P_MASK;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 3adfea9ef0..783aa16a45 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
address &= TARGET_PAGE_MASK;
prot = PAGE_BITS;
if (env->flags & LM32_FLAG_IGNORE_MSB) {
- tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
- TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
+ TARGET_PAGE_SIZE);
} else {
- tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
}
return 0;
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 276fb4bcc9..077b653f24 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -303,12 +303,11 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- M68kCPU *cpu = M68K_CPU(cs);
int prot;
address &= TARGET_PAGE_MASK;
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 11d8aa266d..59c9ad5aef 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -77,7 +77,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
mmu_idx, vaddr, paddr, lu.prot));
- tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
} else {
env->sregs[SR_EAR] = address;
@@ -108,7 +108,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
/* MMU disabled or not available. */
address &= TARGET_PAGE_MASK;
prot = PAGE_BITS;
- tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
return r;
diff --git a/target-mips/helper.c b/target-mips/helper.c
index f3879eddda..b28ae9b033 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -300,7 +300,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
" prot %d\n",
__func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 04b36b78b5..3d0c34dd0a 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -148,7 +148,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
phy = res.phy;
r = 0;
}
- tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
return r;
}
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 4222219acd..750a93636b 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -187,7 +187,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs,
address, rw);
if (ret == TLBRET_MATCH) {
- tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 6a4d6a8025..1cc19162b7 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -400,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
/* Translation is off */
raddr = eaddr;
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -427,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
return 1;
}
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -441,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
if (sr & SR32_T) {
if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
&raddr, &prot) == 0) {
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -522,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 3f405b3cc9..1fefe5881e 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -476,7 +476,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
/* Translation is off */
/* In real mode the top 4 effective address bits are ignored */
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -578,7 +578,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 653e50230e..1771863dff 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1514,7 +1514,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
}
ret = get_physical_address(env, &ctx, address, rw, access_type);
if (ret == 0) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index d4ea7d56d1..aa628b8fe2 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -417,7 +417,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
(uint64_t)vaddr, (uint64_t)raddr, prot);
- tlb_set_page(env, orig_vaddr, raddr, prot,
+ tlb_set_page(cs, orig_vaddr, raddr, prot,
mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 88f69be216..9ebdd5c9b5 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -512,7 +512,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
address &= TARGET_PAGE_MASK;
physical &= TARGET_PAGE_MASK;
- tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 1571c6a026..61afbcf048 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -217,7 +217,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
TARGET_FMT_lx "\n", address, paddr, vaddr);
#endif
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
}
@@ -233,7 +233,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
neverland. Fake/overridden mappings will be flushed when
switching to normal mode. */
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
} else {
if (rw & 2) {
@@ -729,7 +729,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context);
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
}
/* XXX */
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 39ecd98907..9a3786dddb 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -253,7 +253,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
/* Map a single page. */
phys_addr &= TARGET_PAGE_MASK;
address &= TARGET_PAGE_MASK;
- tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 1eec89155c..b531019488 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -77,10 +77,10 @@ void tlb_fill(CPUState *cs,
vaddr, is_write, mmu_idx, paddr, ret);
if (ret == 0) {
- tlb_set_page(env,
- vaddr & TARGET_PAGE_MASK,
- paddr & TARGET_PAGE_MASK,
- access, mmu_idx, page_size);
+ tlb_set_page(cs,
+ vaddr & TARGET_PAGE_MASK,
+ paddr & TARGET_PAGE_MASK,
+ access, mmu_idx, page_size);
} else {
cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);