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authorPeter Maydell <peter.maydell@linaro.org>2020-02-10 12:01:46 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-13 14:30:51 +0000
commitdc7a88d0810ad272bdcd2e0869359af78fdd9114 (patch)
tree9a4c94c9e41811cddbf7a6318e26e6787260e4f2
parent759f0f87e34fe63a475d926ea6db88d11d2cd018 (diff)
downloadqemu-arm-dc7a88d0810ad272bdcd2e0869359af78fdd9114.tar.gz
target/arm: Implement ARMv8.1-VMID16 extensionpull-target-arm-20200213
The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits: * the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is 8 or 16 bits * the VMID field in VTTBR_EL2 is extended to 16 bits * VTCR_EL2.VS lets the guest specify whether to use the full 16 bits, or use the backwards-compatible 8 bits For QEMU implementing this is trivial: * we do not track VMIDs in TLB entries, so we never use the VMID field * we treat any write to VTTBR_EL2, not just a change to the VMID field bits, as a "possible VMID change" that causes us to throw away TLB entries, so that code doesn't need changing * we allow the guest to read/write the VTCR_EL2.VS bit already So all that's missing is the ID register part: report that we support VMID16 in our 'max' CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200210120146.17631-1-peter.maydell@linaro.org
-rw-r--r--target/arm/cpu64.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1359564c55..f0d98bc79d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
cpu->isar.id_aa64mmfr1 = t;
t = cpu->isar.id_aa64mmfr2;