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authorPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:05:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:18:09 +0000
commit718488cb45188dfdb9886342121aa472db66cdf5 (patch)
treea4339072cbfc267edc9b8ac1cc9409848b34f9e2
parentfbd7274266c12d669186ab3382170822468336ef (diff)
downloadqemu-arm-718488cb45188dfdb9886342121aa472db66cdf5.tar.gz
target/arm: Provide ARMv8.4-PMU in '-cpu max'
Set the ID register bits to provide ARMv8.4-PMU (and implicitly also ARMv8.1-PMU) in the 'max' CPU. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- v1->v2: use FIELD_DP64 for 64-bit idreg
-rw-r--r--target/arm/cpu64.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f8f74a7ecd..c945289403 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -703,6 +703,14 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->id_mmfr3 = u;
+ u = cpu->isar.id_aa64dfr0;
+ u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+ cpu->isar.id_aa64dfr0 = u;
+
+ u = cpu->isar.id_dfr0;
+ u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+ cpu->isar.id_dfr0 = u;
+
/*
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
* so do not set MVFR1.FPHP. Strictly speaking this is not legal,