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authorPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:05:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:18:35 +0000
commit65d3a1fd6635ff72aba6497edd19a13ab0bde51e (patch)
tree23842a884c7f6317d6e483b1fe6967226d8c45a3
parentf84baee87d6a7d591d2b20bc3be537f35afcd752 (diff)
downloadqemu-arm-65d3a1fd6635ff72aba6497edd19a13ab0bde51e.tar.gz
target/arm: Use isar_feature function for testing AA32HPD feature
Now we have moved ID_MMFR4 into the ARMISARegisters struct, we can define and use an isar_feature for the presence of the ARMv8.2-AA32HPD feature, rather than open-coding the test. While we're here, correct a comment typo which missed an 'A' from the feature name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/cpu.h5
-rw-r--r--target/arm/helper.c4
2 files changed, 7 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ba97fc75c1..276030a5cf 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3526,6 +3526,11 @@ static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
}
+static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
+}
+
/*
* 64-bit feature tests via id registers.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 492741a2b0..56b1c08f02 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7408,8 +7408,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} else {
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
- /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
- if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) {
+ /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
+ if (cpu_isar_feature(aa32_hpd, cpu)) {
define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
}
}