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authorPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:05:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:18:46 +0000
commit23fee158bc5d7ef7a4ff9d4e8e69303f9e7968da (patch)
treeb2d052851928ebfe31dd1b3cf13dd31d94c592e0
parent65d3a1fd6635ff72aba6497edd19a13ab0bde51e (diff)
downloadqemu-arm-23fee158bc5d7ef7a4ff9d4e8e69303f9e7968da.tar.gz
target/arm: Use FIELD_EX32 for testing 32-bit fields
Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes no difference in behaviour, it's just more consistent.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/cpu.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 276030a5cf..c6af3290ca 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3453,18 +3453,18 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
{
/* Return true if D16-D31 are implemented */
- return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2;
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
}
static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point */
- return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
/*
@@ -3474,32 +3474,32 @@ static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
*/
static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
}
static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
}
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
}
static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
}
static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
}
static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
}
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)