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authorPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:05:46 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-14 17:05:46 +0000
commit14a2dea4ef9bb44b7e4e1fe459b4a3f3546fa8c5 (patch)
treea1c47989d396718c45698790ce58f7fc1fef4ee0
parent37fa9e668e305ad9c0eb5e036d5354e5b719b046 (diff)
downloadqemu-arm-14a2dea4ef9bb44b7e4e1fe459b4a3f3546fa8c5.tar.gz
target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
We already define FIELD macros for ID_DFR0, so use them in the one place where we're doing direct bit value manipulation. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- We have lots of this non-FIELD style in the code, of course; I change this one purely because it otherwise looks a bit odd sat next to the ID_AA64DFR0 line that was changed in the previous patch...
-rw-r--r--target/arm/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 12bf968800..1024f506c5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#endif
} else {
cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
- cpu->id_dfr0 &= ~(0xf << 24);
+ cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}