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authorPeter Maydell <peter.maydell@linaro.org>2016-02-15 17:22:56 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-02-18 18:14:01 +0000
commiteff7f2e48258ddd11baf98d2c027e34d5ffb47ad (patch)
treef39e4155627535b68dccd9f417e69b6ee091c938
parente7f55f6280fa235ad19de05ea003ed8ec818d635 (diff)
downloadqemu-arm-eff7f2e48258ddd11baf98d2c027e34d5ffb47ad.tar.gz
target-arm: Make mode switches from Hyp via CPS and MRS illegal
Mode switches from Hyp to any other mode via the CPS and MRS instructions are illegal mode switches (though obviously switching via exception return is valid). Add this check to bad_mode_switch(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-11-git-send-email-peter.maydell@linaro.org
-rw-r--r--target-arm/helper.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ff5f8955a1..24ea48ecdc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5200,12 +5200,20 @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
/* Helper coprocessor reset function for do-nothing-on-reset registers */
}
-static int bad_mode_switch(CPUARMState *env, int mode)
+static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
{
/* Return true if it is not valid for us to switch to
* this CPU mode (ie all the UNPREDICTABLE cases in
* the ARM ARM CPSRWriteByInstr pseudocode).
*/
+
+ /* Changes to or from Hyp via MSR and CPS are illegal. */
+ if (write_type == CPSRWriteByInstr &&
+ ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
+ mode == ARM_CPU_MODE_HYP)) {
+ return 1;
+ }
+
switch (mode) {
case ARM_CPU_MODE_USR:
case ARM_CPU_MODE_SYS:
@@ -5324,7 +5332,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
if (write_type != CPSRWriteRaw &&
(env->uncached_cpsr & CPSR_M) != CPSR_USER &&
((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
- if (bad_mode_switch(env, val & CPSR_M)) {
+ if (bad_mode_switch(env, val & CPSR_M, write_type)) {
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
* v7, and has defined behaviour in v8:
* + leave CPSR.M untouched