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authorPeter Maydell <peter.maydell@linaro.org>2017-02-20 14:04:43 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-20 14:04:43 +0000
commit9039ac89f8d297e1d18f415778ce457897392eec (patch)
tree9c34af233370152259d720270ae495c1b2031554
parent5bb337cab74e9eda3255557caac5fd076e4a2f85 (diff)
downloadqemu-arm-9039ac89f8d297e1d18f415778ce457897392eec.tar.gz
armv7m: Allow SHCSR writes to change pending and active bits
Implement the NVIC SHCSR write behaviour which allows pending and active status of some exceptions to be changed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/intc/armv7m_nvic.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 718b1a1034..76097b4830 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -755,8 +755,17 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
cpu->env.v7m.ccr = value;
break;
case 0xd24: /* System Handler Control. */
- /* TODO: Real hardware allows you to set/clear the active bits
- under some circumstances. We don't implement this. */
+ s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
+ s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
+ s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
+ s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
+ s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
+ s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
+ s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
+ s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
+ s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
+ s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
+ s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;