diff options
| author | Michael Davidsaver <mdavidsaver@gmail.com> | 2015-11-27 16:34:11 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-04-11 17:31:59 +0100 |
| commit | 27bae8f0e183f27c60c39bea6afa1ba7a35e0e7b (patch) | |
| tree | 93317b1b7c6ac47b4a4fb62d9460529c57ab62eb | |
| parent | 9e63caef04e41a62a6dd378ee02b5938edffde98 (diff) | |
armv7m: Implement M profile default memory map
Add support for the M profile default memory map which is used
if the MPU is not present or disabled.
The main differences in behaviour from implementing this
correctly are that we set the PAGE_EXEC attribute on
the right regions of memory, such that device regions
are not executable.
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
[PMM: rephrased comment and commit message; don't mark
the flash memory region as not-writable]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 35 |
1 files changed, 26 insertions, 9 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index f183f7a1ac..0d7198b709 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8119,18 +8119,35 @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, int32_t address, int *prot) { - *prot = PAGE_READ | PAGE_WRITE; - switch (address) { - case 0xF0000000 ... 0xFFFFFFFF: - if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */ + if (!arm_feature(env, ARM_FEATURE_M)) { + *prot = PAGE_READ | PAGE_WRITE; + switch (address) { + case 0xF0000000 ... 0xFFFFFFFF: + if (regime_sctlr(env, mmu_idx) & SCTLR_V) { + /* hivecs execing is ok */ + *prot |= PAGE_EXEC; + } + break; + case 0x00000000 ... 0x7FFFFFFF: *prot |= PAGE_EXEC; + break; + } + } else { + /* Default system address map for M profile cores. + * The architecture specifies which regions are execute-never; + * at the MPU level no other checks are defined. + */ + switch (address) { + case 0x00000000 ... 0x1fffffff: /* ROM */ + case 0x20000000 ... 0x3fffffff: /* SRAM */ + case 0x60000000 ... 0x7fffffff: /* RAM */ + case 0x80000000 ... 0x9fffffff: /* RAM */ + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + break; + default: /* Peripheral, 2x Device, and System */ + *prot = PAGE_READ | PAGE_WRITE; } - break; - case 0x00000000 ... 0x7FFFFFFF: - *prot |= PAGE_EXEC; - break; } - } static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |