diff options
| author | Sergey Kambalin <sergey.kambalin@auriga.com> | 2023-06-13 00:34:56 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-06-19 15:27:21 +0100 |
| commit | 074259c0f2ac40042dce766d870318cc22f388eb (patch) | |
| tree | b3c5e674788806a0c0c7b303ad236db359e9f4bd | |
| parent | 5dc496363a5bd7bec9cf0287cfbece9b94bcfa9a (diff) | |
hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware propertypull-target-arm-20230619
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230612223456.33824-5-philmd@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com>
[PMD: Split from bigger patch: 3/4]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMM: added a comment about RPI_FIRMWARE_CORE_CLK_RATE
really being SoC-specific]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/misc/bcm2835_property.c | 3 | ||||
| -rw-r--r-- | include/hw/arm/raspi_platform.h | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 2e4fe969bf..4ed9faa54a 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -127,6 +127,9 @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value) case RPI_FIRMWARE_UART_CLK_ID: stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_RATE); break; + case RPI_FIRMWARE_CORE_CLK_ID: + stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_CORE_CLK_RATE); + break; default: stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_DEFAULT_CLK_RATE); diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h index 83f2588fc5..ede98e63c3 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -173,6 +173,11 @@ /* Clock rates */ #define RPI_FIRMWARE_EMMC_CLK_RATE 50000000 #define RPI_FIRMWARE_UART_CLK_RATE 3000000 +/* + * TODO: this is really SoC-specific; we might want to + * set it per-SoC if it turns out any guests care. + */ +#define RPI_FIRMWARE_CORE_CLK_RATE 350000000 #define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000 #endif |