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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-03-27 14:55:22 +0100
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2015-03-30 13:39:38 +0200
commitf1fdaf552974ee2ef6ec1ba3cf1e18c2951533e1 (patch)
treead028a866d5b672767d8362c299985301d023be4
parent627f91b1f80fecc73d00727181a9ddb6162cc30e (diff)
downloadqemu-arm-f1fdaf552974ee2ef6ec1ba3cf1e18c2951533e1.tar.gz
target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
..for address calculation instead address registers. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
-rw-r--r--target-tricore/translate.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index bbcfee9754..54a48cd694 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -4509,14 +4509,14 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_CACHEA_I_POSTINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEA_WI_PREINC:
case OPC2_32_BO_CACHEA_W_PREINC:
case OPC2_32_BO_CACHEA_I_PREINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
@@ -4526,13 +4526,13 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} /* TODO: else raise illegal opcode trap */
break;
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} /* TODO: else raise illegal opcode trap */
break;
case OPC2_32_BO_ST_A_SHORTOFF: