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authorPeter Maydell <peter.maydell@linaro.org>2015-03-31 09:56:48 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-03-31 09:56:48 +0100
commitadbeb458eece2263039e5a1f6501b87ae3713319 (patch)
treecd745355a8632a02fd7cc280a277feeb2fa6f42b
parentd4892d935b035c2220827145524d0cf0573d1fea (diff)
parentf1fdaf552974ee2ef6ec1ba3cf1e18c2951533e1 (diff)
downloadqemu-arm-adbeb458eece2263039e5a1f6501b87ae3713319.tar.gz
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150330' into staging
TriCore bugfixes # gpg: Signature made Mon Mar 30 12:40:50 2015 BST using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20150330: target-tricore: fix CACHEA/I_POSTINC/PREINC using data register.. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-tricore/translate.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index bbcfee9754..54a48cd694 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -4509,14 +4509,14 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_CACHEA_I_POSTINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEA_WI_PREINC:
case OPC2_32_BO_CACHEA_W_PREINC:
case OPC2_32_BO_CACHEA_I_PREINC:
/* instruction to access the cache, but we still need to handle
the addressing mode */
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
@@ -4526,13 +4526,13 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} /* TODO: else raise illegal opcode trap */
break;
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
- tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} /* TODO: else raise illegal opcode trap */
break;
case OPC2_32_BO_ST_A_SHORTOFF: