diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-02-10 18:12:31 +0000 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-03-24 09:45:28 +0100 |
| commit | 00e1754ff1f6294a29e08398a120663eac723216 (patch) | |
| tree | 66d18c62fa4d0ea3b80be904a0df326145ba3824 | |
| parent | 2b9d09bb3c44de934de03864d56ddd8a38ed863a (diff) | |
target-tricore: fix RRPW_DEXTR using wrong reg
RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the
other way round. This also fixes that the result of the first shift was not
saved in a temp and could overwrite registers that were needed for the second
shift.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| -rw-r--r-- | target-tricore/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 989a047991..bbcfee9754 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8044,8 +8044,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); } else { temp = tcg_temp_new(); - tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16); - tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16); + tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16); + tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16); tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); tcg_temp_free(temp); } |