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authorPeter Maydell <peter.maydell@linaro.org>2018-07-24 12:42:27 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-07-24 12:42:31 +0100
commit4556438d0cdf8d83eda18551df7821e3fb1714a9 (patch)
tree17ae06b0e754e817b68f3ba33e97645a9b29d737
parent7d9728371f8c9bd6787108aae57d983d01325bb2 (diff)
downloadqemu-arm-4556438d0cdf8d83eda18551df7821e3fb1714a9.tar.gz
target/arm: Provide accessor functions for HCR_EL2.{IMO,FMO,AMO}
The IMO, FMO and AMO bits in HCR_EL2 are defined to "behave as 1 for all purposes other than direct reads" if HCR_EL2.TGE is set and HCR_EL2.E2H is 0, and to "behave as 0 for all purposes other than direct reads" if HCR_EL2.TGE is set and HRC_EL2.E2H is 1. To avoid having to check E2H and TGE everywhere where we test IMO and FMO, provide accessors arm_hcr_el2_imo(), arm_hcr_el2_fmo()and arm_hcr_el2_amo(). We don't implement ARMv8.1-VHE yet, so the E2H case will never be true, but we include the logic to save effort when we eventually do get to that. (Note that in several of these callsites the change doesn't actually make a difference as either the callsite is handling TGE specially anyway, or the CPU can't get into that situation with TGE set; we change everywhere for consistency.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/intc/arm_gicv3_cpuif.c19
-rw-r--r--target/arm/cpu.h64
-rw-r--r--target/arm/helper.c6
3 files changed, 71 insertions, 18 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 2a60568d82..068a8e8e9b 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -85,7 +85,10 @@ static bool icv_access(CPUARMState *env, int hcr_flags)
* * access if NS EL1 and either IMO or FMO == 1:
* CTLR, DIR, PMR, RPR
*/
- return (env->cp15.hcr_el2 & hcr_flags) && arm_current_el(env) == 1
+ bool flagmatch = ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) ||
+ ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env));
+
+ return flagmatch && arm_current_el(env) == 1
&& !arm_is_secure_below_el3(env);
}
@@ -1549,8 +1552,8 @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* No need to include !IsSecure in route_*_to_el2 as it's only
* tested in cases where we know !IsSecure is true.
*/
- route_fiq_to_el2 = env->cp15.hcr_el2 & HCR_FMO;
- route_irq_to_el2 = env->cp15.hcr_el2 & HCR_IMO;
+ route_fiq_to_el2 = arm_hcr_el2_fmo(env);
+ route_irq_to_el2 = arm_hcr_el2_imo(env);
switch (arm_current_el(env)) {
case 3:
@@ -1893,7 +1896,7 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env,
switch (el) {
case 1:
if (arm_is_secure_below_el3(env) ||
- ((env->cp15.hcr_el2 & (HCR_IMO | HCR_FMO)) == 0)) {
+ (arm_hcr_el2_imo(env) == 0 && arm_hcr_el2_fmo(env) == 0)) {
r = CP_ACCESS_TRAP_EL3;
}
break;
@@ -1933,7 +1936,7 @@ static CPAccessResult gicv3_dir_access(CPUARMState *env,
static CPAccessResult gicv3_sgi_access(CPUARMState *env,
const ARMCPRegInfo *ri, bool isread)
{
- if ((env->cp15.hcr_el2 & (HCR_IMO | HCR_FMO)) &&
+ if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) &&
arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) {
/* Takes priority over a possible EL3 trap */
return CP_ACCESS_TRAP_EL2;
@@ -1958,8 +1961,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env,
if (env->cp15.scr_el3 & SCR_FIQ) {
switch (el) {
case 1:
- if (arm_is_secure_below_el3(env) ||
- ((env->cp15.hcr_el2 & HCR_FMO) == 0)) {
+ if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) {
r = CP_ACCESS_TRAP_EL3;
}
break;
@@ -1998,8 +2000,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env,
if (env->cp15.scr_el3 & SCR_IRQ) {
switch (el) {
case 1:
- if (arm_is_secure_below_el3(env) ||
- ((env->cp15.hcr_el2 & HCR_IMO) == 0)) {
+ if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) {
r = CP_ACCESS_TRAP_EL3;
}
break;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efb2a8d3f3..4289c33ef4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1229,6 +1229,12 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
#define HCR_RW (1ULL << 31)
#define HCR_CD (1ULL << 32)
#define HCR_ID (1ULL << 33)
+#define HCR_E2H (1ULL << 34)
+/*
+ * When we actually implement ARMv8.1-VHE we should add HCR_E2H to
+ * HCR_MASK and then clear it again if the feature bit is not set in
+ * hcr_write().
+ */
#define HCR_MASK ((1ULL << 34) - 1)
#define SCR_NS (1U << 0)
@@ -2234,6 +2240,54 @@ bool write_cpustate_to_list(ARMCPU *cpu);
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+/**
+ * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO.
+ * Depending on the values of HCR_EL2.E2H and TGE, this may be
+ * "behaves as 1 for all purposes other than direct read/write" or
+ * "behaves as 0 for all purposes other than direct read/write"
+ */
+static inline bool arm_hcr_el2_imo(CPUARMState *env)
+{
+ switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
+ case HCR_TGE:
+ return true;
+ case HCR_TGE | HCR_E2H:
+ return false;
+ default:
+ return env->cp15.hcr_el2 & HCR_IMO;
+ }
+}
+
+/**
+ * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO.
+ */
+static inline bool arm_hcr_el2_fmo(CPUARMState *env)
+{
+ switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
+ case HCR_TGE:
+ return true;
+ case HCR_TGE | HCR_E2H:
+ return false;
+ default:
+ return env->cp15.hcr_el2 & HCR_FMO;
+ }
+}
+
+/**
+ * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO.
+ */
+static inline bool arm_hcr_el2_amo(CPUARMState *env)
+{
+ switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
+ case HCR_TGE:
+ return true;
+ case HCR_TGE | HCR_E2H:
+ return false;
+ default:
+ return env->cp15.hcr_el2 & HCR_AMO;
+ }
+}
+
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
unsigned int target_el)
{
@@ -2261,15 +2315,13 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
break;
case EXCP_VFIQ:
- if (secure || !(env->cp15.hcr_el2 & HCR_FMO)
- || (env->cp15.hcr_el2 & HCR_TGE)) {
+ if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
/* VFIQs are only taken when hypervized and non-secure. */
return false;
}
return !(env->daif & PSTATE_F);
case EXCP_VIRQ:
- if (secure || !(env->cp15.hcr_el2 & HCR_IMO)
- || (env->cp15.hcr_el2 & HCR_TGE)) {
+ if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
/* VIRQs are only taken when hypervized and non-secure. */
return false;
}
@@ -2308,7 +2360,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
* to the CPSR.F setting otherwise we further assess the state
* below.
*/
- hcr = (env->cp15.hcr_el2 & HCR_FMO);
+ hcr = arm_hcr_el2_fmo(env);
scr = (env->cp15.scr_el3 & SCR_FIQ);
/* When EL3 is 32-bit, the SCR.FW bit controls whether the
@@ -2325,7 +2377,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
* when setting the target EL, so it does not have a further
* affect here.
*/
- hcr = (env->cp15.hcr_el2 & HCR_IMO);
+ hcr = arm_hcr_el2_imo(env);
scr = false;
break;
default:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e2930e9938..699189ebd7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6342,15 +6342,15 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
switch (excp_idx) {
case EXCP_IRQ:
scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
- hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
+ hcr = arm_hcr_el2_imo(env);
break;
case EXCP_FIQ:
scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
- hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
+ hcr = arm_hcr_el2_fmo(env);
break;
default:
scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
- hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
+ hcr = arm_hcr_el2_amo(env);
break;
};