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authorSergey Fedorov <serge.fdrv@gmail.com>2015-07-06 10:05:43 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-07-06 10:05:43 +0100
commit2a6332d968297266dbabf9d33f959e3a5efdd0f9 (patch)
tree42109e197fe96c7ee1192d1bd7dab498399f1dc2
parentf50a1640fb82708a5d528dee1ace42a224b95b15 (diff)
downloadqemu-arm-2a6332d968297266dbabf9d33f959e3a5efdd0f9.tar.gz
target-arm: fix write helper for TLBI ALLE1IS
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs in the same Inner Sharable domain, not just on the current CPU. So we must use tlbiall_is_write() here. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1435676538-31345-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aa341599cf..b87afe7cde 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2441,7 +2441,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_write },
+ .writefn = tlbiall_is_write },
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW,