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authorMax Filippov <jcmvbkbc@gmail.com>2011-10-16 02:56:01 +0400
committerBlue Swirl <blauwirbel@gmail.com>2011-10-16 10:39:27 +0000
commit7f65f4b059c4a91b97a032801a4c137e87612c6a (patch)
treef024b50602cd1739fa82c23d6d868879f177a80d
parent3aeaea654afb1b45a99798f87c143392b2994712 (diff)
downloadqemu-arm-7f65f4b059c4a91b97a032801a4c137e87612c6a.tar.gz
target-xtensa: increase xtensa options accuracy
- add separate options for each operation in the MISC_OP; - add an option for MULSH/MULUH; - put S32C1I under conditional store option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--target-xtensa/cpu.h6
-rw-r--r--target-xtensa/translate.c14
2 files changed, 12 insertions, 8 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index b43e565254..df168d5790 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -52,9 +52,13 @@ enum {
XTENSA_OPTION_EXTENDED_L32R,
XTENSA_OPTION_16_BIT_IMUL,
XTENSA_OPTION_32_BIT_IMUL,
+ XTENSA_OPTION_32_BIT_IMUL_HIGH,
XTENSA_OPTION_32_BIT_IDIV,
XTENSA_OPTION_MAC16,
- XTENSA_OPTION_MISC_OP,
+ XTENSA_OPTION_MISC_OP_NSA,
+ XTENSA_OPTION_MISC_OP_MINMAX,
+ XTENSA_OPTION_MISC_OP_SEXT,
+ XTENSA_OPTION_MISC_OP_CLAMPS,
XTENSA_OPTION_COPROCESSOR,
XTENSA_OPTION_BOOLEAN,
XTENSA_OPTION_FP_COPROCESSOR,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 70bea62396..1688bb2462 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -1116,13 +1116,13 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 14: /*NSAu*/
- HAS_OPTION(XTENSA_OPTION_MISC_OP);
+ HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
gen_window_check2(dc, RRR_S, RRR_T);
gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
break;
case 15: /*NSAUu*/
- HAS_OPTION(XTENSA_OPTION_MISC_OP);
+ HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
gen_window_check2(dc, RRR_S, RRR_T);
gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
break;
@@ -1434,7 +1434,7 @@ static void disas_xtensa_insn(DisasContext *dc)
case 10: /*MULUHi*/
case 11: /*MULSHi*/
- HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
{
TCGv_i64 r = tcg_temp_new_i64();
TCGv_i64 s = tcg_temp_new_i64();
@@ -1521,7 +1521,7 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 2: /*SEXTu*/
- HAS_OPTION(XTENSA_OPTION_MISC_OP);
+ HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
gen_window_check2(dc, RRR_R, RRR_S);
{
int shift = 24 - RRR_T;
@@ -1540,7 +1540,7 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 3: /*CLAMPSu*/
- HAS_OPTION(XTENSA_OPTION_MISC_OP);
+ HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
gen_window_check2(dc, RRR_R, RRR_S);
{
TCGv_i32 tmp1 = tcg_temp_new_i32();
@@ -1568,7 +1568,7 @@ static void disas_xtensa_insn(DisasContext *dc)
case 5: /*MAXu*/
case 6: /*MINUu*/
case 7: /*MAXUu*/
- HAS_OPTION(XTENSA_OPTION_MISC_OP);
+ HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
{
static const TCGCond cond[] = {
@@ -1921,7 +1921,7 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 14: /*S32C1Iy*/
- HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
+ HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
gen_window_check2(dc, RRI8_S, RRI8_T);
{
int label = gen_new_label();