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authorJan Kiszka <jan.kiszka@siemens.com>2011-10-07 09:19:44 +0200
committerBlue Swirl <blauwirbel@gmail.com>2011-10-16 11:11:05 +0000
commit51d9e939b8120d76feb096aeff04368683784541 (patch)
tree708ed1ac9b744513f8fe30058891d8752f333264
parent78ef2b6989fb20eb7eee3a5cef66655ea1d19175 (diff)
downloadqemu-arm-51d9e939b8120d76feb096aeff04368683784541.tar.gz
i8259: Update IRQ state after reset
MIPS and PPC users of the i8259 output signal expect us to report state updates also after reset. As no consumer (including the master PIC) can misinterpret the deassert as an activation event, it is safe to simply update the IRQ state after reset. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--hw/i8259.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/hw/i8259.c b/hw/i8259.c
index b7a011fb69..3498c6bf66 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -283,6 +283,7 @@ static void pic_reset(void *opaque)
s->init4 = 0;
s->single_mode = 0;
/* Note: ELCR is not reset */
+ pic_update_irq(s->pics_state);
}
static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
@@ -298,8 +299,6 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
if (val & 0x10) {
/* init */
pic_reset(s);
- /* deassert a pending interrupt */
- qemu_irq_lower(s->pics_state->pics[0].int_out);
s->init_state = 1;
s->init4 = val & 1;
s->single_mode = val & 2;