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authorRichard Henderson <rth@twiddle.net>2010-02-16 14:15:28 -0800
committerBlue Swirl <blauwirbel@gmail.com>2010-02-20 08:33:52 +0000
commit791d1262e27becc435702417d0f7c99c894ff6fe (patch)
treef37514461f0c2434a9ae87396d260af4fd38e41d
parent241cbed4a992e31e718f56f831d7dd30fec5b55b (diff)
downloadqemu-arm-791d1262e27becc435702417d0f7c99c894ff6fe.tar.gz
tcg: Optional target implementation of ORC.
Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--tcg/tcg-op.h11
-rw-r--r--tcg/tcg-opc.h6
2 files changed, 17 insertions, 0 deletions
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 447878db01..6ae1760298 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1715,20 +1715,31 @@ static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
+#ifdef TCG_TARGET_HAS_orc_i32
+ tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
+#else
TCGv_i32 t0;
t0 = tcg_temp_new_i32();
tcg_gen_not_i32(t0, arg2);
tcg_gen_or_i32(ret, arg1, t0);
tcg_temp_free_i32(t0);
+#endif
}
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
+#ifdef TCG_TARGET_HAS_orc_i64
+ tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
+ tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+ tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
TCGv_i64 t0;
t0 = tcg_temp_new_i64();
tcg_gen_not_i64(t0, arg2);
tcg_gen_or_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
+#endif
}
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 6d855a767d..34cdba5b58 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -112,6 +112,9 @@ DEF2(neg_i32, 1, 1, 0, 0)
#ifdef TCG_TARGET_HAS_andc_i32
DEF2(andc_i32, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_orc_i32
+DEF2(orc_i32, 1, 2, 0, 0)
+#endif
#if TCG_TARGET_REG_BITS == 64
DEF2(mov_i64, 1, 1, 0, 0)
@@ -191,6 +194,9 @@ DEF2(neg_i64, 1, 1, 0, 0)
#ifdef TCG_TARGET_HAS_andc_i64
DEF2(andc_i64, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_orc_i64
+DEF2(orc_i64, 1, 2, 0, 0)
+#endif
#endif
/* QEMU specific */