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authorPeter Maydell <peter.maydell@linaro.org>2012-09-26 17:51:30 +0100
committerPeter Maydell <peter.maydell@linaro.org>2012-09-26 18:13:40 +0100
commit877bc3c5403f006e43978c9a5cbea0101c96363c (patch)
tree3cf87b047583a6236b67c6a947c2f322a223db28
parentf8bf746d1a8afb399ea6980ca8e4b74a549e9151 (diff)
downloadqemu-arm-877bc3c5403f006e43978c9a5cbea0101c96363c.tar.gz
tcg/arm: Implement movcond_i32
Implement movcond_i32 for ARM, as the sequence cmp c1, c2 movCC dst, v1 movCC dst, v2 (where the two conditions are each others' inverses). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--tcg/arm/tcg-target.c10
-rw-r--r--tcg/arm/tcg-target.h2
2 files changed, 11 insertions, 1 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index a83b295da7..e38fd65f2d 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1587,6 +1587,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_movi_i32:
tcg_out_movi32(s, COND_AL, args[0], args[1]);
break;
+ case INDEX_op_movcond_i32:
+ /* Constraints mean that v2 is always in the same register as dest,
+ * so we only need to do "if condition passed, move v1 to dest".
+ */
+ tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0,
+ args[1], args[2], const_args[2]);
+ tcg_out_dat_rI(s, tcg_cond_to_arm_cond[args[5]],
+ ARITH_MOV, args[0], 0, args[3], const_args[3]);
+ break;
case INDEX_op_add_i32:
c = ARITH_ADD;
goto gen_arith;
@@ -1798,6 +1807,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_brcond_i32, { "r", "rI" } },
{ INDEX_op_setcond_i32, { "r", "r", "rI" } },
+ { INDEX_op_movcond_i32, { "r", "r", "rI", "rI", "0" } },
/* TODO: "r", "r", "r", "r", "ri", "ri" */
{ INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index e2299cadd3..0df33520f8 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -73,7 +73,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_GUEST_BASE