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authorPeter Maydell <peter.maydell@linaro.org>2018-07-16 11:04:24 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-07-16 11:04:24 +0100
commit633e824037210a60c0b23d6c0e42420db1fe4c08 (patch)
treed29a6853dbb95540b7d10489cce4bcd2c7f4fc86
parentb808d2001d41352948f84affa62be66910537107 (diff)
parent6730df0514d3aec35e646ff9833fbe8b05fd0776 (diff)
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180716' into staging
ppc patch queue 2018-07-16 Here's my first hard freeze pull request for qemu-3.0. This contains an assortment of bugfixes. Several are for regressions, others are for bugs that I think are significant enough to address during hard freeze. # gpg: Signature made Mon 16 Jul 2018 09:28:37 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.0-20180716: sm501: Fix warning about unreachable code sam460ex: Correct use after free error etsec: fix IRQ (un)masking ppc/xics: fix ICP reset path spapr: Correct inverted test in spapr_pc_dimm_node() sm501: Update screen on frame buffer address change Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/display/sm501.c4
-rw-r--r--hw/intc/xics.c14
-rw-r--r--hw/net/fsl_etsec/etsec.c68
-rw-r--r--hw/net/fsl_etsec/etsec.h2
-rw-r--r--hw/net/fsl_etsec/registers.h10
-rw-r--r--hw/net/fsl_etsec/rings.c12
-rw-r--r--hw/ppc/sam460ex.c3
-rw-r--r--hw/ppc/spapr.c2
8 files changed, 66 insertions, 49 deletions
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 3661a89f60..874260a143 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -1024,7 +1024,7 @@ static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value,
if (res) {
SM501_DPRINTF("sm501 i2c : transfer failed"
" i=%d, res=%d\n", i, res);
- s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0);
+ s->i2c_status |= SM501_I2C_STATUS_ERROR;
return;
}
}
@@ -1235,6 +1235,7 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
if (value & 0x8000000) {
qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n");
}
+ s->do_full_update = true;
break;
case SM501_DC_PANEL_FB_OFFSET:
s->dc_panel_fb_offset = value & 0x3FF03FF0;
@@ -1298,6 +1299,7 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
if (value & 0x8000000) {
qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n");
}
+ s->do_full_update = true;
break;
case SM501_DC_CRT_FB_OFFSET:
s->dc_crt_fb_offset = value & 0x3FF03FF0;
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index b9f1a3c972..c90c893228 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -291,7 +291,7 @@ static const VMStateDescription vmstate_icp_server = {
},
};
-static void icp_reset(void *dev)
+static void icp_reset(DeviceState *dev)
{
ICPState *icp = ICP(dev);
@@ -303,6 +303,13 @@ static void icp_reset(void *dev)
qemu_set_irq(icp->output, 0);
}
+static void icp_reset_handler(void *dev)
+{
+ DeviceClass *dc = DEVICE_GET_CLASS(dev);
+
+ dc->reset(dev);
+}
+
static void icp_realize(DeviceState *dev, Error **errp)
{
ICPState *icp = ICP(dev);
@@ -345,7 +352,7 @@ static void icp_realize(DeviceState *dev, Error **errp)
return;
}
- qemu_register_reset(icp_reset, dev);
+ qemu_register_reset(icp_reset_handler, dev);
vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
}
@@ -354,7 +361,7 @@ static void icp_unrealize(DeviceState *dev, Error **errp)
ICPState *icp = ICP(dev);
vmstate_unregister(NULL, &vmstate_icp_server, icp);
- qemu_unregister_reset(icp_reset, dev);
+ qemu_unregister_reset(icp_reset_handler, dev);
}
static void icp_class_init(ObjectClass *klass, void *data)
@@ -363,6 +370,7 @@ static void icp_class_init(ObjectClass *klass, void *data)
dc->realize = icp_realize;
dc->unrealize = icp_unrealize;
+ dc->reset = icp_reset;
}
static const TypeInfo icp_info = {
diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
index 9da1932970..0b66274ce3 100644
--- a/hw/net/fsl_etsec/etsec.c
+++ b/hw/net/fsl_etsec/etsec.c
@@ -49,6 +49,28 @@ static const int debug_etsec;
} \
} while (0)
+/* call after any change to IEVENT or IMASK */
+void etsec_update_irq(eTSEC *etsec)
+{
+ uint32_t ievent = etsec->regs[IEVENT].value;
+ uint32_t imask = etsec->regs[IMASK].value;
+ uint32_t active = ievent & imask;
+
+ int tx = !!(active & IEVENT_TX_MASK);
+ int rx = !!(active & IEVENT_RX_MASK);
+ int err = !!(active & IEVENT_ERR_MASK);
+
+ DPRINTF("%s IRQ ievent=%"PRIx32" imask=%"PRIx32" %c%c%c",
+ __func__, ievent, imask,
+ tx ? 'T' : '_',
+ rx ? 'R' : '_',
+ err ? 'E' : '_');
+
+ qemu_set_irq(etsec->tx_irq, tx);
+ qemu_set_irq(etsec->rx_irq, rx);
+ qemu_set_irq(etsec->err_irq, err);
+}
+
static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
{
eTSEC *etsec = opaque;
@@ -139,31 +161,6 @@ static void write_rbasex(eTSEC *etsec,
etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
}
-static void write_ievent(eTSEC *etsec,
- eTSEC_Register *reg,
- uint32_t reg_index,
- uint32_t value)
-{
- /* Write 1 to clear */
- reg->value &= ~value;
-
- if (!(reg->value & (IEVENT_TXF | IEVENT_TXF))) {
- qemu_irq_lower(etsec->tx_irq);
- }
- if (!(reg->value & (IEVENT_RXF | IEVENT_RXF))) {
- qemu_irq_lower(etsec->rx_irq);
- }
-
- if (!(reg->value & (IEVENT_MAG | IEVENT_GTSC | IEVENT_GRSC | IEVENT_TXC |
- IEVENT_RXC | IEVENT_BABR | IEVENT_BABT | IEVENT_LC |
- IEVENT_CRL | IEVENT_FGPI | IEVENT_FIR | IEVENT_FIQ |
- IEVENT_DPE | IEVENT_PERR | IEVENT_EBERR | IEVENT_TXE |
- IEVENT_XFUN | IEVENT_BSY | IEVENT_MSRO | IEVENT_MMRD |
- IEVENT_MMRW))) {
- qemu_irq_lower(etsec->err_irq);
- }
-}
-
static void write_dmactrl(eTSEC *etsec,
eTSEC_Register *reg,
uint32_t reg_index,
@@ -178,9 +175,7 @@ static void write_dmactrl(eTSEC *etsec,
} else {
/* Graceful receive stop now */
etsec->regs[IEVENT].value |= IEVENT_GRSC;
- if (etsec->regs[IMASK].value & IMASK_GRSCEN) {
- qemu_irq_raise(etsec->err_irq);
- }
+ etsec_update_irq(etsec);
}
}
@@ -191,9 +186,7 @@ static void write_dmactrl(eTSEC *etsec,
} else {
/* Graceful transmit stop now */
etsec->regs[IEVENT].value |= IEVENT_GTSC;
- if (etsec->regs[IMASK].value & IMASK_GTSCEN) {
- qemu_irq_raise(etsec->err_irq);
- }
+ etsec_update_irq(etsec);
}
}
@@ -222,7 +215,16 @@ static void etsec_write(void *opaque,
switch (reg_index) {
case IEVENT:
- write_ievent(etsec, reg, reg_index, value);
+ /* Write 1 to clear */
+ reg->value &= ~value;
+
+ etsec_update_irq(etsec);
+ break;
+
+ case IMASK:
+ reg->value = value;
+
+ etsec_update_irq(etsec);
break;
case DMACTRL:
@@ -337,6 +339,8 @@ static void etsec_reset(DeviceState *d)
MII_SR_EXTENDED_STATUS | MII_SR_100T2_HD_CAPS | MII_SR_100T2_FD_CAPS |
MII_SR_10T_HD_CAPS | MII_SR_10T_FD_CAPS | MII_SR_100X_HD_CAPS |
MII_SR_100X_FD_CAPS | MII_SR_100T4_CAPS;
+
+ etsec_update_irq(etsec);
}
static ssize_t etsec_receive(NetClientState *nc,
diff --git a/hw/net/fsl_etsec/etsec.h b/hw/net/fsl_etsec/etsec.h
index 30c828e241..877988572e 100644
--- a/hw/net/fsl_etsec/etsec.h
+++ b/hw/net/fsl_etsec/etsec.h
@@ -163,6 +163,8 @@ DeviceState *etsec_create(hwaddr base,
qemu_irq rx_irq,
qemu_irq err_irq);
+void etsec_update_irq(eTSEC *etsec);
+
void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr);
void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr);
ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size);
diff --git a/hw/net/fsl_etsec/registers.h b/hw/net/fsl_etsec/registers.h
index c4ed2b9d62..f085537ecd 100644
--- a/hw/net/fsl_etsec/registers.h
+++ b/hw/net/fsl_etsec/registers.h
@@ -74,6 +74,16 @@ extern const eTSEC_Register_Definition eTSEC_registers_def[];
#define IEVENT_RXC (1 << 30)
#define IEVENT_BABR (1 << 31)
+/* Mapping between interrupt pin and interrupt flags */
+#define IEVENT_RX_MASK (IEVENT_RXF | IEVENT_RXB)
+#define IEVENT_TX_MASK (IEVENT_TXF | IEVENT_TXB)
+#define IEVENT_ERR_MASK (IEVENT_MAG | IEVENT_GTSC | IEVENT_GRSC | IEVENT_TXC | \
+ IEVENT_RXC | IEVENT_BABR | IEVENT_BABT | IEVENT_LC | \
+ IEVENT_CRL | IEVENT_FGPI | IEVENT_FIR | IEVENT_FIQ | \
+ IEVENT_DPE | IEVENT_PERR | IEVENT_EBERR | IEVENT_TXE | \
+ IEVENT_XFUN | IEVENT_BSY | IEVENT_MSRO | IEVENT_MMRD | \
+ IEVENT_MMRW)
+
#define IMASK_RXFEN (1 << 7)
#define IMASK_GRSCEN (1 << 8)
#define IMASK_RXBEN (1 << 15)
diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c
index d0f93eebfc..337a55fc95 100644
--- a/hw/net/fsl_etsec/rings.c
+++ b/hw/net/fsl_etsec/rings.c
@@ -152,17 +152,7 @@ static void ievent_set(eTSEC *etsec,
{
etsec->regs[IEVENT].value |= flags;
- if ((flags & IEVENT_TXB && etsec->regs[IMASK].value & IMASK_TXBEN)
- || (flags & IEVENT_TXF && etsec->regs[IMASK].value & IMASK_TXFEN)) {
- qemu_irq_raise(etsec->tx_irq);
- RING_DEBUG("%s Raise Tx IRQ\n", __func__);
- }
-
- if ((flags & IEVENT_RXB && etsec->regs[IMASK].value & IMASK_RXBEN)
- || (flags & IEVENT_RXF && etsec->regs[IMASK].value & IMASK_RXFEN)) {
- qemu_irq_raise(etsec->rx_irq);
- RING_DEBUG("%s Raise Rx IRQ\n", __func__);
- }
+ etsec_update_irq(etsec);
}
static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len)
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index e2b7028843..0999efcc1e 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -269,11 +269,12 @@ static int sam460ex_load_device_tree(hwaddr addr,
exit(1);
}
fdt = load_device_tree(filename, &fdt_size);
- g_free(filename);
if (!fdt) {
error_report("Couldn't load dtb file `%s'", filename);
+ g_free(filename);
exit(1);
}
+ g_free(filename);
/* Manipulate device tree in memory. */
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3f5e1d3ec2..421b2dd09b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -665,7 +665,7 @@ static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
- if (pcdimm_info->addr >= addr &&
+ if (addr >= pcdimm_info->addr &&
addr < (pcdimm_info->addr + pcdimm_info->size)) {
return pcdimm_info->node;
}