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authorPeter Maydell <peter.maydell@linaro.org>2015-07-16 12:47:28 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-08-07 15:48:48 +0100
commit1dfdf35927c7ea7e027c1a1352b03d11a9257b1d (patch)
treecfadc8145d8fe99302735e97fe3ec758235c327a
parente752040f45bfbd64765a9faeb49f19093563536c (diff)
downloadqemu-arm-1dfdf35927c7ea7e027c1a1352b03d11a9257b1d.tar.gz
hw/arm/virt: Wire up secure timer interrupt
Wire up the secure timer interrupt. Since we've defined that the plain old physical timer is the NS timer, we can drop the now-out-of-date comment about QEMU not having TZ. Use a data-driven loop to wire up the timer interrupts, since we now have four of them and the code is the same for each. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-4-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--hw/arm/virt.c28
1 files changed, 15 insertions, 13 deletions
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 94694d6530..d5a84175c9 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -391,20 +391,22 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
for (i = 0; i < smp_cpus; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
- /* physical timer; we wire it up to the non-secure timer's ID,
- * since a real A15 always has TrustZone but QEMU doesn't.
+ int irq;
+ /* Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs we use for the virt board.
*/
- qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_NS_EL1_IRQ));
- /* virtual timer */
- qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_VIRT_IRQ));
- /* Hypervisor timer. */
- qdev_connect_gpio_out(cpudev, 2,
- qdev_get_gpio_in(gicdev,
- ppibase + ARCH_TIMER_NS_EL2_IRQ));
+ const int timer_irq[] = {
+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
+ };
+
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
+ qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(gicdev,
+ ppibase + timer_irq[irq]));
+ }
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,