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authorPeter Maydell <peter.maydell@linaro.org>2020-12-03 14:21:44 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-02-15 13:16:13 +0000
commitf4c15bc8a6ba90b928daf7b9c3a5de2c10ab9bc3 (patch)
tree4f330ecd9db8ba4d6fedc58ff5af0bfa2f85dfe3
parent34f994257be5b0384bbfd1fc73a6fff9c116b3e2 (diff)
downloadqemu-arm-f4c15bc8a6ba90b928daf7b9c3a5de2c10ab9bc3.tar.gz
hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
In the SSE-300, the format of the SYS_CONFIG0 register has changed again; pass through the correct value to the SYSINFO register block device. We drop the old SysConfigFormat enum, which was implemented in the hope that different flavours of SSE would share the same format; since they all seem to be different and we now have an sse_version enum to key off, just use that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/arm/armsse.c21
1 files changed, 9 insertions, 12 deletions
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 67fa4ffe34..113a783a46 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -24,12 +24,6 @@
#include "hw/irq.h"
#include "hw/qdev-clock.h"
-/* Format of the System Information block SYS_CONFIG register */
-typedef enum SysConfigFormat {
- IoTKitFormat,
- SSE200Format,
-} SysConfigFormat;
-
struct ARMSSEInfo {
const char *name;
uint32_t sse_version;
@@ -37,7 +31,6 @@ struct ARMSSEInfo {
int num_cpus;
uint32_t sys_version;
uint32_t cpuwait_rst;
- SysConfigFormat sys_config_format;
bool has_mhus;
bool has_ppus;
bool has_cachectrl;
@@ -78,7 +71,6 @@ static const ARMSSEInfo armsse_variants[] = {
.num_cpus = 1,
.sys_version = 0x41743,
.cpuwait_rst = 0,
- .sys_config_format = IoTKitFormat,
.has_mhus = false,
.has_ppus = false,
.has_cachectrl = false,
@@ -93,7 +85,6 @@ static const ARMSSEInfo armsse_variants[] = {
.num_cpus = 2,
.sys_version = 0x22041743,
.cpuwait_rst = 2,
- .sys_config_format = SSE200Format,
.has_mhus = true,
.has_ppus = true,
.has_cachectrl = true,
@@ -108,13 +99,13 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
/* Return the SYS_CONFIG value for this SSE */
uint32_t sys_config;
- switch (info->sys_config_format) {
- case IoTKitFormat:
+ switch (info->sse_version) {
+ case ARMSSE_IOTKIT:
sys_config = 0;
sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12);
break;
- case SSE200Format:
+ case ARMSSE_SSE200:
sys_config = 0;
sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
@@ -125,6 +116,12 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
sys_config = deposit32(sys_config, 28, 4, 2);
}
break;
+ case ARMSSE_SSE300:
+ sys_config = 0;
+ sys_config = deposit32(sys_config, 0, 4, info->sram_banks);
+ sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width);
+ sys_config = deposit32(sys_config, 16, 3, 3); /* CPU0 = Cortex-M55 */
+ break;
default:
g_assert_not_reached();
}