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authorPeter Maydell <peter.maydell@linaro.org>2021-02-04 11:28:07 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-02-15 13:15:14 +0000
commita73c2317af0c7a3c31cee479377712c84686ef83 (patch)
treeb432077ba25fb672623f0ecc87776f2d0cb4349f
parente18818ca78637739609c51f442ade97e1d0b5c40 (diff)
downloadqemu-arm-a73c2317af0c7a3c31cee479377712c84686ef83.tar.gz
hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board
The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-rw-r--r--hw/arm/mps2-tz.c23
1 files changed, 18 insertions, 5 deletions
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 976f5f5c68..9add1453cc 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -77,6 +77,8 @@ struct MPS2TZMachineClass {
MPS2TZFPGAType fpga_type;
uint32_t scc_id;
uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
+ uint32_t len_oscclk;
+ const uint32_t *oscclk;
const char *armsse_type;
};
@@ -115,6 +117,12 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
/* Slow 32Khz S32KCLK frequency in Hz */
#define S32KCLK_FRQ (32 * 1000)
+static const uint32_t an505_oscclk[] = {
+ 40000000,
+ 24580000,
+ 25000000,
+};
+
/* Create an alias of an entire original MemoryRegion @orig
* located at @base in the memory map.
*/
@@ -213,17 +221,18 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
MPS2SCC *scc = opaque;
DeviceState *sccdev;
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
+ int i;
object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC);
sccdev = DEVICE(scc);
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
- /* This will need to be per-FPGA image eventually */
- qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
- qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000);
- qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000);
- qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
+ qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk);
+ for (i = 0; i < mmc->len_oscclk; i++) {
+ g_autofree char *propname = g_strdup_printf("oscclk[%d]", i);
+ qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]);
+ }
sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
}
@@ -676,6 +685,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
mmc->scc_id = 0x41045050;
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
+ mmc->oscclk = an505_oscclk;
+ mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
mmc->armsse_type = TYPE_IOTKIT;
}
@@ -692,6 +703,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
mmc->scc_id = 0x41045210;
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
+ mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */
+ mmc->len_oscclk = ARRAY_SIZE(an505_oscclk);
mmc->armsse_type = TYPE_SSE200;
}