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authorPeter Maydell <peter.maydell@linaro.org>2021-02-05 13:58:19 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-02-15 13:15:15 +0000
commit61c574ab8c8b53ade0d7f5a7fd6e2fd846d27851 (patch)
treefc6cecb5cdaa29560a1cb54959657775cc86e2be
parentcc6b6b91413857c7d46c4b3b8c310f01dfda19ca (diff)
downloadqemu-arm-61c574ab8c8b53ade0d7f5a7fd6e2fd846d27851.tar.gz
docs/system/arm/mps2.rst: Document the new mps3-an524 board
Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-rw-r--r--docs/system/arm/mps2.rst24
1 files changed, 18 insertions, 6 deletions
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index 8c5b5f1fe0..601ccea15c 100644
--- a/docs/system/arm/mps2.rst
+++ b/docs/system/arm/mps2.rst
@@ -1,12 +1,15 @@
-Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
-================================================================================================================
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``)
+=========================================================================================================================================
These board models all use Arm M-profile CPUs.
-The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
-FPGA but is otherwise the same as the 2). Since the CPU itself
-and most of the devices are in the FPGA, the details of the board
-as seen by the guest depend significantly on the FPGA image.
+The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
+bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
+FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
+
+Since the CPU itself and most of the devices are in the FPGA, the
+details of the board as seen by the guest depend significantly on the
+FPGA image.
QEMU models the following FPGA images:
@@ -22,12 +25,21 @@ QEMU models the following FPGA images:
Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
``mps2-an521``
Dual Cortex-M33 as documented in Arm Application Note AN521
+``mps3-an524``
+ Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524
Differences between QEMU and real hardware:
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
if zbt_boot_ctrl is always zero)
+- AN524 remapping of low memory to either BRAM or to QSPI flash is
+ unimplemented (QEMU always maps this to BRAM, ignoring the
+ SCC CFG_REG0 memory-remap bit)
- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
visible difference is that the LAN9118 doesn't support checksum
offloading
+- QEMU does not model the QSPI flash in MPS3 boards as real QSPI
+ flash, but only as simple ROM, so attempting to rewrite the flash
+ from the guest will fail
+- QEMU does not model the USB controller in MPS3 boards