diff options
| author | Ard Biesheuvel <ardb@kernel.org> | 2022-11-22 16:55:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-11-22 16:10:25 +0000 |
| commit | 15f8f4671afd22491ce99d28a296514717fead4f (patch) | |
| tree | 6f1ef41980c05fa2d08e9bbe1a091c086c5c585f | |
| parent | 26ba00cf58e9f21b08fff4c691ce7e9bb21dd123 (diff) | |
target/arm: Use signed quantity to represent VMSAv8-64 translation levelpull-target-arm-20221122
The LPA2 extension implements 52-bit virtual addressing for 4k and 16k
translation granules, and for the former, this means an additional level
of translation is needed. This means we start counting at -1 instead of
0 when doing a walk, and so 'level' is now a signed quantity, and should
be typed as such. So turn it from uint32_t into int32_t.
This avoids a level of -1 getting misinterpreted as being >= 3, and
terminating a page table walk prematurely with a bogus output address.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/ptw.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8ca468d65b..f812734bfb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1172,7 +1172,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, ARMCPU *cpu = env_archcpu(env); ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_secure = ptw->in_secure; - uint32_t level; + int32_t level; ARMVAParameters param; uint64_t ttbr; hwaddr descaddr, indexmask, indexmask_grainsize; @@ -1302,7 +1302,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ uint32_t sl0 = extract32(tcr, 6, 2); uint32_t sl2 = extract64(tcr, 33, 1); - uint32_t startlevel; + int32_t startlevel; bool ok; /* SL2 is RES0 unless DS=1 & 4kb granule. */ |