diff options
| author | Evgeny Iakovlev <eiakovlev@linux.microsoft.com> | 2023-01-05 23:12:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-01-13 13:19:36 +0000 |
| commit | 08899b5c68a55a3780d707e2464073c8f2670d31 (patch) | |
| tree | 494b94d46d8089c9cbe09c23da5678c1c39f975e | |
| parent | 543d02267150aef71763fb2baaccef8eb9e5042a (diff) | |
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabledpull-target-arm-20230113
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is
enabled and exposed to the guest. As a result EL3 writes of that bit are
ignored.
Cc: qemu-stable@nongnu.org
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Message-id: 20230105221251.17896-4-eiakovlev@linux.microsoft.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index cee3804354..22ea8fbe36 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1866,6 +1866,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_sme, cpu)) { valid_mask |= SCR_ENTP2; } + if (cpu_isar_feature(aa64_hcx, cpu)) { + valid_mask |= SCR_HXEN; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { |